tag:blogger.com,1999:blog-82185528355657094092024-03-17T13:39:44.540+05:30VHDL ProgrammingLearn All about VHDL Programming with Learn and Grow CommunityLearn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.comBlogger143125tag:blogger.com,1999:blog-8218552835565709409.post-60461603910233988872023-09-06T19:44:00.001+05:302023-09-06T19:44:15.118+05:30VHDL Basics : Insights Sequential and Concurrent Statements - No More Confusion [Beginner’s Guide] - Part ii<p> </p><p style="text-align: center;"><a href="https://youtu.be/eY5TsS-NfuQ" target="_blank"><b><span style="font-size: medium;">Click Here for Video Tutorial - VHDL Basics : Insights Sequential and Concurrent Statements - No More Confusion [Beginner’s Guide] - Part ii</span></b></a></p><p style="text-align: center;"><br /></p><p style="text-align: center;"><br /></p><p style="text-align: center;"></p><div class="separator" style="clear: both; text-align: center;"><a href="https://youtu.be/eY5TsS-NfuQ" style="margin-left: 1em; margin-right: 1em;" target="_blank"><img alt="" data-original-height="1080" data-original-width="1920" height="225" src="https://blogger.googleusercontent.com/img/a/AVvXsEgsEYpmbYrI1h1A33AfBRZRd1Xa_VVuQwiUIhD-lKwqOTu1grgv4KPB3avpicSBvEZhgQP7SZfHLJDa3n69l60-kPk4nf5Za-awKnE6it3tXfXdaFt_YefJbuMHFMY5r4mHQ2TWiqFmkOZBuw6WfGAnk2fosHJ8BAxcJ5C2Pzl6H1lrEUh-lWbyny2s-rU7=w400-h225" width="400" /></a></div><br /><br /><p></p><p style="text-align: center;"><br /></p><p style="text-align: left;"><span style="background-color: white; color: #0d0d0d; font-family: Roboto, Noto, sans-serif; font-size: 15px; white-space-collapse: preserve;">This is the Part ii of last Video "VHDL Basics : Insights Sequential and Concurrent Statements - No More Confusion [Beginner’s Guide]", for deeper understanding, and it is very important to have deeper insights on Sequential and Concurrent statement, if you are designing anything in VHDL or Verilog HDL.
In this comprehensive tutorial, we will cover everything you need to know about VHDL sequential and concurrent statements. Sequential statements allow us to execute code in a step-by-step manner, while concurrent statements offer a more parallel execution approach.
Now dig down little more with an example - </span><span style="color: #0d0d0d; font-family: Roboto, Noto, sans-serif;"><span style="font-size: 15px; white-space-collapse: preserve;">Here I written two architectures with identical statements, top left architecture will execute those statements concurrently, but bottom right architecture will execute statements sequentially. Here if you noticed that in both the statements the output signal is same, that is Dout. And we are saying Dout gets the value of logical AND of inputs and in the second statement we says Dout gets the value of logical OR of inputs.</span></span></p><p style="text-align: left;"><span style="background-color: white; font-size: 15px; white-space-collapse: preserve;"><span style="color: #0d0d0d; font-family: Roboto, Noto, sans-serif;">architecture Concurrent of my_design is
begin
Dout <= A AND B ;
Dout <= A OR B;
end Concurrent;
---------------------------------------------
architecture Sequential of my_design is
begin
process (A,B,C)
begin
Dout <= A AND B ;
Dout <= A OR B;
end process;
end Sequential;</span></span></p><p style="text-align: left;"><span style="background-color: white; color: #0d0d0d; font-family: Roboto, Noto, sans-serif; font-size: 15px; white-space-collapse: preserve;">
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</span></p><div><span style="background-color: white; font-size: 15px; white-space-collapse: preserve;"><span style="color: #0d0d0d; font-family: Roboto, Noto, sans-serif;">Do you see any problem in this structure ? If your answer is No, than try to figure out the output if input A is ‘0’ and input ‘B’ is 1, so the output of the AND gate is digital ‘0’ and the output of the OR gate is digital ‘1’, and you shorted them both these outputs. This is not good for the hardware, right? This is called contention, because two set of logics are driving the same signal and this is not allowed to synthesized as well, so You will not be able to synthesized your design, and you will probably get the synthesizer error in such cases.
Now let’s talk about the sequential statements – Here we have the same set of statements, but these are now executing sequentially, means 1st statement executes first which says Output Dout gets the value of logical AND of inputs.
So we made a AND gate. Now execute the 2nd statement which says Output Dout gets the value of logical OR of inputs. So here this second statement override the output signal Dout. Which means at the end of this statement Dout has the value of OR function. And the first statement of AND function get’s ignore completely. And we will get the only functionality of OR gate.</span></span></div><div><span style="background-color: white; font-size: 15px; white-space-collapse: preserve;"><span style="color: #0d0d0d; font-family: Roboto, Noto, sans-serif;"><br /></span></span></div><div><span style="background-color: white; font-size: 15px; white-space-collapse: preserve;"><span style="color: #0d0d0d; font-family: Roboto, Noto, sans-serif;"><br /></span></span></div><div style="text-align: justify;"><a href="https://youtu.be/eY5TsS-NfuQ" style="margin-left: 1em; margin-right: 1em; text-align: center;" target="_blank"><img alt="" data-original-height="1080" data-original-width="1920" height="225" src="https://blogger.googleusercontent.com/img/a/AVvXsEgsEYpmbYrI1h1A33AfBRZRd1Xa_VVuQwiUIhD-lKwqOTu1grgv4KPB3avpicSBvEZhgQP7SZfHLJDa3n69l60-kPk4nf5Za-awKnE6it3tXfXdaFt_YefJbuMHFMY5r4mHQ2TWiqFmkOZBuw6WfGAnk2fosHJ8BAxcJ5C2Pzl6H1lrEUh-lWbyny2s-rU7=w400-h225" width="400" /></a></div><div><span style="background-color: white; font-size: 15px; white-space-collapse: preserve;"><span style="color: #0d0d0d; font-family: Roboto, Noto, sans-serif;"><br /></span></span></div><div><span style="background-color: white; font-size: 15px; white-space-collapse: preserve;"><span style="color: #0d0d0d; font-family: Roboto, Noto, sans-serif;"><br /></span></span></div><div><span style="background-color: white; font-size: 15px; white-space-collapse: preserve;"><span style="color: #0d0d0d; font-family: Roboto, Noto, sans-serif;"><br /></span></span></div><div><span style="background-color: white; white-space-collapse: preserve;"><span style="color: #0d0d0d; font-family: Roboto, Noto, sans-serif; font-size: medium;"><b>Subscribe to "Learn And Grow Community"
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In this slide we will have little more understanding about those sequential statements and concurrent statement in VHDL.</p><p><br /></p><p>Let’s take the same example, If you notice it is the same code we have used in our last session where we have 2 inputs, input A & input B and 1 output. We have one internal signal S as well. Where signal S was the output of a NAND gate and later that signal S wired up with the not gate and output of the NOT gate connected to the output Dout.</p><p><br /></p><p>For this design We had written both type of statements in our VHDL code, which are concurrent statements and sequential statements.</p><p>Let’s explore the area where we used process and written some conditional statements like if-else, these statements inside the process executes sequentially, and hence called sequential statements in VHDL. The second area is where we written a statement outside the process, within the architecture, these statements will execute concurrently and hence called concurrent statements in VHDL. Likewise in this example, in VHDL we can write both type of statements which are sequential and concurrent statements to describe the functionality of our digital system.</p><p><br /></p><p>Interesting part is, all the statements inside the process are sequential statements and executes sequentially but the process statement itself executes concurrently with other concurrent statements. Here, we have 2 concurrent statements 1 is very clear, I believe, and 2nd concurrent statement will be the whole process from start of process to end of process.</p><p><br /></p><p>If you noticed we terminated the process statement at the end of process with the semicolon not in the line where we started our process, this means although there are multiple lines inside the process which are separately terminated but the process itself is only terminated where the process ends and hence it’s treated as single statement of concurrent statement. I know this may take little time to have deeper understanding, but we will be discussing lot more on this topic later to make this clear.</p><p><br /></p><p>But first let's explore the difference between execution style of concurrent statements and sequential statements.</p><p><br /></p><p>Sequential statements are very much like software languages. These statements execute sequentially that means at the start statement 1 will execute and then statement 2 will execute than statement 3 will execute and so on.</p><p><br /></p><p>We also have the concurrent statements in VHDL, these statements are very likely to a hardware model like a schematic design. All the concurrent statements execute simultaneously, just like hardware. </p><p><br /></p><p>So if you have Concurrent statement 1 and statement 2 and 3 and 4 and so on… and all these statements executes concurrently, which means when the concurrent statement 1 is executing at the same time statement 4 is executing, similarly at the same time statement 2 or statement 3 are executing. I mean all are executing at the same time, so this is important to know that the sequence or order of the statements not really matter if your statement executing concurrently, and you can write them anywhere within the architecture without thinking of the sequence. And the results will be the same.</p><div><br /></div><div><br /></div><div><div class="separator" style="clear: both; text-align: center;"><div class="separator" style="clear: both; text-align: center;"><a href="https://youtu.be/6ef5kA8XKLc" style="margin-left: 1em; margin-right: 1em;" target="_blank"><img alt="Click here for Video Tutorial" data-original-height="1080" data-original-width="1920" height="225" src="https://blogger.googleusercontent.com/img/a/AVvXsEi6JPw-CAUcmxbSMydAGVUAS4Bk0DBMzIUUGqkKOfHyHG8Hr3egFFR5LdWy1BgfGFgONetWEaL7L1MVPrWyD4J8V1uxy-cDIgSb_-eRIGsaQ4TQaZJK93EMGSBlBoeFGMJuwyQhbhwco1wPKaAbW5ly5YuUSVi2e_BudzNzg4LeTXAlRBmErutLau6Pj1wS=w400-h225" title="Click here for Video Tutorial" width="400" /></a></div><br /></div><br /><br /></div><p><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;">In this comprehensive tutorial, we will cover everything you need to know about VHDL sequential and concurrent statements. Sequential statements allow us to execute code in a step-by-step manner, while concurrent statements offer a more parallel execution approach.
Welcome to this beginner's guide on VHDL basics, where we will dive into the concepts of sequential and concurrent statements in VHDL. If you've ever been confused about these fundamental aspects of VHDL programming, this video is perfect for you.
We will start by explaining the differences between sequential and concurrent statements, providing clear examples and illustrations to eliminate any confusion. By the end of this video, you will have a solid understanding of how to effectively utilize sequential and concurrent statements in your VHDL designs.
This guide is suitable for beginners who have some basic knowledge of VHDL. We will go step-by-step and explain each concept thoroughly, ensuring that you grasp the fundamentals before moving on to more advanced topics.
Make sure to subscribe to our channel for more informative videos on VHDL programming and digital design. Don't forget to hit the notification bell to stay updated with our latest uploads. If you have any questions or suggestions, feel free to leave them in the comments section below.</span></p><p><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;"><br /></span></p><p><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;"><br /></span></p><p><span style="background-color: white; white-space-collapse: preserve;"><span face="Roboto, Noto, sans-serif" style="color: #0d0d0d; font-size: medium;"><b>Youtube : <a href="https://www.youtube.com/@Learnandgrowcommunity">https://www.youtube.com/@Learnandgrowcommunity</a>
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You can treat them like interconnection between two logical units or wires in simple terms.</span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;"><br /></span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">Till now, we were talking about the signals which are in the port list inside the entity description, that means we were defining the input or the output pin of our module, But think of the wires which interconnects inside our logical design and those we wanted to use inside our functional description to connect two elements. </span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;"><br /></span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">In VHDL terms we define them with the keyword “Signal” and these need to be defined inside the architecture.</span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;"><br /></span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">The main difference between the port signals which we define in the entity and another which we are defining the architecture is that, Signals from the port list are the interface pins of your module as input or output, and can be used inside the architecture associated with that entity, but the signals which we define inside the architecture, are not actually the interface pins but we wanted to use them internally and these signals can only works inside that architecture.</span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;"><br /></span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">In VHDL we do that by declaring the signals in the architecture between the architecture and begin statement as I am mentioning in the example.</span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;"><br /></span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">In this example inside the Video, Look over the schematic where first we are doing a NAND function between input A and input B, than we are connecting the output of NAND gate to a NOT gate and the output of Not gate is our final output. Simple. Right.</span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">Now look over the wire which is connecting the output of the NAND gate an input to the NOT gate, We call this interconnection or wire. And in terms of VHDL we are calling this signal.</span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">Now if you noticed, this signal is neither the input interface of you module nor the output interface of your module but it is just laying inside the module.</span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;"><br /></span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">So let’s declare the internal signal than,</span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">We declare the internal Signal, named as S and defined it’s data type as BIT. After this declaration now we can use this signal S in our architecture anywhere and can connect different parts of our function.</span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;"><br /></span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">Let’s explore little our code now, Here we have some sequential statements inside the process body, that if both the inputs, these are input A and input B are equal to 1 than our internal signal S will get the value of 0, and if any input is ‘0’ than our internal signal S will get the value ‘1’, </span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;"><br /></span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">Now if you had taken a note that this conditional statement acts simply like a NAND Gate and our internal signal S gets the function of NAND gate, and to get the function of AND gate in the output Dout, We inverted the signal S with a not gate and the output of the NOT gate is our final output Dout. And This output Dout is the output of our module.</span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;"><br /></span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">So let me give a quick brief what we did here, We are designed a simple AND gate, that means Output Dout will be ‘1’ if both inputs are ‘1’ else the output Dout will be ‘0’ – </span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">So, First we defined the entity which has 2 inputs, input A and input B and 1 output Dout. </span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">Than we declared a signal inside the architecture which will act as a internal signal. And inside the process body, we write the behavior of a NAND gate, and moved the result into our internal signal S.</span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;"><br /></span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">Now in the concurrent statement, outside the process we used the not gate to invert the value of internal signal S and than moved that to our final output Dout. Note that Dout is the output of our interface which we declared in the entity.</span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;"><br /></span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">So that was the basic idea of HDL that we describe multiple behaviors and than wire them together using the internal signals.</span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;"><br /></span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="background-color: white; font-size: 13.2px;"></span></span></p><p><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="color: #222222;"><span style="font-size: 13.2px;">At that moment, Don’t be confused with concurrent statement and sequential statement because we will be covering them later in this series, but just understand at the moment that anything which we are writing inside the process will execute sequentially and those statements which are outside the process body will execute concurrently. </span></span></p><div><br /></div><div><div class="separator" style="clear: both; text-align: center;"><a href="https://youtu.be/5QTTDNAvaM0" style="margin-left: 1em; margin-right: 1em;" target="_blank"><img alt="" data-original-height="1080" data-original-width="1920" height="225" src="https://blogger.googleusercontent.com/img/a/AVvXsEhxQ882RUeOZg98djBMWjKtQeWWagUzpuuXQyjboWLQ5w3Ec9_NT1uuE8mEMK6hp4hE0qkJVp2kFjgEHFtDZzgA1Lc8CkVudMC4WTAO9LrotGGfiAzD_aeBCC2JR-S375wSAKWoUB0rulYTq1NacPUponPy_wyeljRgyuAsepqA6QJEyRbtYz6Lajpp6Muw=w400-h225" width="400" /></a></div><br /><br /></div><p><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;">Welcome to VHDL Signal Syntax: A Short & Easy Guide for Beginners! If you've ever been confused about VHDL signal syntax, this video is perfect for you. Designed specifically for beginners, we'll cover all the essentials of VHDL signal syntax in a simple and straightforward manner.
In this tutorial, we'll dive into VHDL and demystify the signal syntax, ensuring that you have a solid foundation to build upon. We'll walk you through the fundamental concepts, providing clear explanations and examples along the way.
Whether you're new to VHDL or looking to brush up on your skills, this beginner's guide has got you covered. By the end, you'll have a clear understanding of VHDL signal syntax, enabling you to write efficient and error-free code.
Here's what you'll learn:
Introduction to VHDL signal syntax
Syntax rules and guidelines for defining signals
Signal declaration and assignment
Types of signals and their usage
Handling and manipulating signals in VHDL
Real-world examples to reinforce your understanding
If you're ready to unravel the mysteries of VHDL signal syntax, click play and let's get started!</span></p><p><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;"><br /></span></p><p><span style="background-color: white; font-size: 15px; white-space-collapse: preserve;"><span face="Roboto, Noto, sans-serif" style="color: #0d0d0d;">Youtube : <a href="https://www.youtube.com/@Learnandgrowcommunity">https://www.youtube.com/@Learnandgrowcommunity</a>
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We call this interface of our module or digital system. So, we need to write VHDL code for all inputs and outputs of our digital system to tell the tool about the interface of our module.</p><p><br /></p><p>The Second item we need to define the functionality of our digital system. So in this section you will write a VHDL code to define what you wanted to get from your digital system, and how it will be achieved. This can be the behavior definition from the sequential statements or the structure design or can be set of concurrent statements.</p><p><br /></p><p>Once you complete these 2 basic needs, you will have a complete VHDL design for your digital system.</p><div><br /></div><div><div>Let’s combine the entity unit and the architecture unit to get our complete VHDL design. </div><div><br /></div><div>This complete design has both the interface description as entity and the behavioral description as architecture and this complete component can be correctly synthesized and place and route into the FPGA.</div><div><br /></div><div>We normally put both the entity unit and the architecture unit in the same file, and we prefer to put entity before the architecture for easy readability.</div></div><div><br /></div><div><div class="separator" style="clear: both; text-align: center;"><br /></div><div>entity MUX is</div><div><span style="white-space: normal;"><span style="white-space: pre;"> </span>port (<span style="white-space: pre;"> </span>A <span style="white-space: pre;"> </span>: in<span style="white-space: pre;"> </span>bit ;</span></div><div><span style="white-space: normal;"><span style="white-space: pre;"> </span>B <span style="white-space: pre;"> </span>: in<span style="white-space: pre;"> </span>bit ;</span></div><div><span style="white-space: normal;"><span style="white-space: pre;"> </span>Sel <span style="white-space: pre;"> </span>: in<span style="white-space: pre;"> </span>bit ;</span></div><div><span style="white-space: normal;"><span style="white-space: pre;"> </span>Dout <span style="white-space: pre;"> </span>: out<span style="white-space: pre;"> </span>bit) ;</span></div><div>end MUX;</div><div><br /></div><div>architecture MUX_Design of MUX is</div><div>Begin</div><div><br /></div><div><span style="white-space: normal;"><span style="white-space: pre;"> </span>process (A,B,Sel)</span></div><div><span style="white-space: normal;"><span style="white-space: pre;"> </span>begin</span></div><div><span style="white-space: normal;"><span style="white-space: pre;"> </span>if (SEL=‘0') then</span></div><div><span style="white-space: normal;"><span style="white-space: pre;"> </span>Dout <= A ;</span></div><div><span style="white-space: normal;"><span style="white-space: pre;"> </span>else</span></div><div><span style="white-space: normal;"><span style="white-space: pre;"> </span>Dout <= B ;</span></div><div><span style="white-space: normal;"><span style="white-space: pre;"> </span>end if ;</span></div><div><span style="white-space: normal;"><span style="white-space: pre;"> </span>end process ;</span></div><div><br /></div><div>end MUX_Design ;</div><br /></div><div><br /></div><div><br /></div><div><br /></div><div><br /></div><div><br /></div><div><div class="separator" style="clear: both; text-align: center;"><a href="https://youtu.be/XYtdHoussmY" style="margin-left: 1em; margin-right: 1em;" target="_blank"><img alt="Click Here For Video Tutorial" data-original-height="1080" data-original-width="1920" height="225" src="https://blogger.googleusercontent.com/img/a/AVvXsEjCvEnH93_MIem9sp01YZOlU0gixq_9yT-4ivCW6XLckQjBNqjK24o0vkUoKq4E89RZmCMwlHnlOMsmYJ5augVuF4-CCORjQluDobbamn5Zn8lgP6rCr50L_fjcF3zd8KBhVLf7A9DtlISCwOwy8zGYo6pdUFEsJjDwdOONDM2Ojbm30BWVplOcitCt_Oz7=w400-h225" width="400" /></a></div><br /><br /></div><div><br /></div><p><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;">Welcome to the ultimate beginner's guide for Your First VHDL Design! In this video, we will dive into the fundamentals of VHDL Entity and Architecture and provide you with a comprehensive understanding of the topic. Whether you are new to VHDL or looking to refresh your knowledge, this guide is designed to help you get started and pave your way to becoming an expert VHDL designer.
In this tutorial, we will cover the basics of VHDL, starting with the VHDL Entity and its crucial role in the design process. You will learn how to define and describe the inputs and outputs of your VHDL design using the Entity section, providing the necessary specifications for your project.
Moving on, we will explore the VHDL Architecture, which defines the actual implementation of your design. Through a step-by-step walkthrough, you will discover how to construct the architecture block by block, ensuring a well-structured and functional VHDL design.
To make the learning experience more practical, we will dive into real-world examples and demonstrate each concept using a popular VHDL software tool. You'll witness the transition from theory to practice, gaining hands-on experience in VHDL design.
With this beginner's guide, you'll not only grasp the essentials of VHDL Entity and Architecture but also acquire the ability to kickstart your own VHDL designs, opening up a wide range of possibilities in digital circuit design.
Subscribe to our channel for more exciting VHDL tutorials and stay tuned for upcoming videos in this series where we will explore advanced VHDL concepts and applications.</span></p><p><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;"><br /></span></p><p><span style="background-color: white; font-size: 15px; white-space-collapse: preserve;"><span face="Roboto, Noto, sans-serif" style="color: #0d0d0d;">Youtube : <a href="https://www.youtube.com/@Learnandgrowcommunity">https://www.youtube.com/@Learnandgrowcommunity</a>
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We start by introducing the fundamentals of FPGA design, explaining the benefits and versatility of using FPGAs in various applications. From there, we explore the wide range of design tools available, from popular industry-standard software like Xilinx Vivado and Altera Quartus Prime to open-source alternatives like GHDL and Icarus Verilog. We highlight the strengths and features of each toolset, enabling you to choose the most suitable one for your projects.
With a solid foundation in FPGA design and tools, we then delve into the VHDL (VHSIC Hardware Description Language) design flow. From understanding the basics of VHDL syntax to implementing complex digital designs, we provide step-by-step explanations and practical demonstrations. You'll learn about entity and architecture design, the importance of libraries, and how to simulate and synthesize VHDL code for your FPGA.
To ensure a holistic learning experience, we discuss common challenges and pitfalls in FPGA design and provide valuable troubleshooting tips. We also touch upon advanced topics like FPGA optimization techniques, timing analysis, and physical implementation considerations.
So, whether you're a student, hobbyist, or professional looking to enhance your FPGA design skills, this tutorial is the ultimate resource to get started on your journey. Join us now and unlock the vast potential of FPGA design tools and the VHDL design flow!
FPGA design tools, VHDL design flow, FPGA development, Xilinx Vivado, Altera Quartus Prime, VHDL, Verilog, VHDL syntax, digital design, entity architecture, libraries, simulate VHDL code, synthesize VHDL code, FPGA optimization techniques, timing analysis, physical implementation, FPGA design skills.</span></p><p><span face="Roboto, Arial, sans-serif" style="background-color: white; color: #131313; font-size: 14px; white-space-collapse: preserve;"><br /></span></p><p><span face="Roboto, Arial, sans-serif" style="background-color: white; color: #131313; font-size: 14px; white-space-collapse: preserve;"><br /></span></p><p><span face="Roboto, Arial, sans-serif" style="background-color: white; color: #131313; font-size: 14px; white-space-collapse: preserve;">Don't miss out on this VHDL revolution! Join us today and unlock endless possibilities in the realm of digital design. Subscribe to our channel for more exciting tutorials and stay ahead in the ever-evolving world of technology.</span></p><p><span style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;">Subscribe to Learn and Grow Community for Regular updates.
Subscribe to our community for more informative videos and guidance. Stay tuned for tutorials, tips, and tricks to enhance your skills. Hit the notification bell to never miss an update.</span></p><p><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;"><br /></span></p><p><span style="background-color: white;"><span face="Roboto, Noto, sans-serif"><span style="color: #0000ee;"><span style="font-size: 15px; white-space-collapse: preserve;"><u>Youtube : https://www.youtube.com/@Learnandgrowcommunity
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</span></span></p><div><span style="background-color: white; font-size: 15px; white-space-collapse: preserve;"><br /></span></div><p><span style="background-color: white; font-size: 14px; white-space-collapse: preserve;"><span face="Roboto, Arial, sans-serif" style="color: #131313;">We're excited to announce that we're launching Learn and Grow Community, a community of learners who are passionate about skill development and growth. and Peoples Who believes that Learning and self-improvement or skill up yourself is the key to grow in life and career in the long way, than Subscribe "Learn and Grow Community" today <a href="https://www.youtube.com/@LearnAndGrowCommunity" target="_blank">(youtube.com\@learnandgrowcommunity</a>) and be a part of the learn and Grow Community!</span></span></p>Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com0tag:blogger.com,1999:blog-8218552835565709409.post-64453037889497257802023-08-27T12:35:00.004+05:302023-08-27T13:08:18.330+05:30VHDL - Language for Hardware Design : Don’t Miss Out On The VHDL Revolution- Learn It Today!<p><span style="background-color: white;"><br /></span></p><p><span style="background-color: white;"><br /></span></p><p><a href="https://www.youtube.com/watch?v=zRE-npI8WLA" target="_blank"><span style="font-size: large;"><span style="background-color: white;"> Click Here for Video Tutorial - </span>VHDL - Language for Hardware Design : Don’t Miss Out On The VHDL Revolution- Learn It Today!</span></a></p><p><span style="background-color: white;"><br /></span></p><p><span style="background-color: white;"></span></p><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/a/AVvXsEhYEOew7gANTEPNHbF09S1YJDMfaMC_SwgI0rDGSsvyB-0f4g9lRPcXNM4WsQAFGUPShHpSm6YmF4ppaxAi_glZ-vq-CNBxidqGcZYRsZx6bkVD1RNKPAG7nDt4OSMAZIwbuRRrXY_0iKyvE0efka5PAuZevGPsqmOrko9eMLD08126rhi3QJuExIdgdA8A" style="margin-left: 1em; margin-right: 1em;"><img alt="" data-original-height="1080" data-original-width="1920" height="180" src="https://blogger.googleusercontent.com/img/a/AVvXsEhYEOew7gANTEPNHbF09S1YJDMfaMC_SwgI0rDGSsvyB-0f4g9lRPcXNM4WsQAFGUPShHpSm6YmF4ppaxAi_glZ-vq-CNBxidqGcZYRsZx6bkVD1RNKPAG7nDt4OSMAZIwbuRRrXY_0iKyvE0efka5PAuZevGPsqmOrko9eMLD08126rhi3QJuExIdgdA8A" width="320" /></a></div><br /><br /><p></p><p><span style="background-color: white;"></span></p><div class="separator" style="clear: both; text-align: center;"><a href="https://www.youtube.com/watch?v=zRE-npI8WLA" style="text-align: left;" target="_blank"><span style="font-size: large;"><span style="background-color: white;"> Click Here for Video Tutorial - </span>VHDL - Language for Hardware Design : Don’t Miss Out On The VHDL Revolution- Learn It Today!</span></a></div><br /><br /><p></p><p><span face="Roboto, Arial, sans-serif" style="background-color: white; color: #131313; font-size: 14px; white-space-collapse: preserve;">VHDL - Language for Hardware Design :
Don’t Miss Out On The VHDL Revolution - Learn It Today!
Are you fascinated by the world of digital design? Interested in learning the powerful hardware description language, VHDL? Look no further! In this comprehensive beginner's guide, we bring you an opportunity to embark on a journey to master VHDL and join the revolution of digital design.
VHDL (VHSIC Hardware Description Language) serves as a crucial tool for designing and describing digital systems. Whether you are an aspiring engineer, a student, or a professional seeking to enhance your skill set, this tutorial will provide you with a solid foundation in VHDL.
Throughout this video series, we delve into the fundamentals of VHDL, explaining its syntax, data types, operators, and control structures. We'll explore various modeling techniques, such as data flow and behavioral modeling, enabling you to conceptualize complex digital circuits effortlessly. You'll also gain insights into designing finite state machines (FSMs) and understanding the importance of testbenches for verification.
To make your learning experience interactive and engaging, we offer practical examples and guide you through hands-on projects. By the end of this tutorial, you'll be equipped with the knowledge and confidence to design your digital systems using VHDL.
Don't miss out on this VHDL revolution! Join us today and unlock endless possibilities in the realm of digital design. Subscribe to our channel for more exciting tutorials and stay ahead in the ever-evolving world of technology.</span></p><p><span style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;">Subscribe to Learn and Grow Community for Regular updates.
Subscribe to our community for more informative videos and guidance. Stay tuned for tutorials, tips, and tricks to enhance your skills. Hit the notification bell to never miss an update.</span></p><p><span style="background-color: white; font-size: 15px; white-space-collapse: preserve;"><span face="Roboto, Noto, sans-serif" style="color: #0d0d0d;"><a href="https://www.youtube.com/watch?v=IQxTvjjnb7g">https://www.youtube.com/watch?v=IQxTvjjnb7g</a></span></span></p><p><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;"><br /></span></p><p><span style="background-color: white; font-size: 15px; white-space-collapse: preserve;"><span face="Roboto, Noto, sans-serif" style="color: #0d0d0d;"><a href="https://www.youtube.com/@Learnandgrowcommunity">https://www.youtube.com/@Learnandgrowcommunity</a>
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</span></span></p><div><span style="background-color: white; font-size: 15px; white-space-collapse: preserve;"><br /></span></div><p><span style="background-color: white; font-size: 14px; white-space-collapse: preserve;"><span face="Roboto, Arial, sans-serif" style="color: #131313;">We're excited to announce that we're launching Learn and Grow Community, a community of learners who are passionate about skill development and growth. and Peoples Who believes that Learning and self-improvement or skill up yourself is the key to grow in life and career in the long way, than Subscribe "Learn and Grow Community" today <a href="https://www.youtube.com/@LearnAndGrowCommunity" target="_blank">(youtube.com\@learnandgrowcommunity</a>) and be a part of the learn and Grow Community!</span></span></p>Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com0tag:blogger.com,1999:blog-8218552835565709409.post-25352063344825024052023-08-27T12:15:00.007+05:302023-08-27T12:25:40.212+05:30VHDL - Language for Hardware Design : Know why you need to learn VHDL?<div class="separator" style="clear: both; text-align: center;"><div class="separator" style="clear: both;"><br /></div><div class="separator" style="clear: both;"><br /></div><div class="separator" style="clear: both;"><br /></div><div class="separator" style="clear: both;"><a href="https://www.youtube.com/watch?v=IQxTvjjnb7g" style="text-align: left;" target="_blank"><span style="font-size: large;">Click Here for Video Tutorial - VHDL - Language for Hardware Design : Know why you need to learn VHDL?</span></a></div><div class="separator" style="clear: both;"><br /></div><br /><br /></div><div class="separator" style="clear: both; text-align: center;"><div class="separator" style="clear: both; text-align: center;"><div class="separator" style="clear: both; text-align: center;"><div class="separator" style="clear: both; text-align: center;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/a/AVvXsEjbqrXKka1SWJADLrxney7C8AI7g-YnwLj65Ws1YWN8F38ncJGAJeu_PJY9CPpESFywhn8nrJZyrr_hYaHZg9SKXlw4MoRmb4G34PCq1C8DlkrNiq4ujdqNarb7vX_EXN8sRql5BYjH9KgaJrB-KygFe5E7E7Q1KC4mgh85D3WfsJkKVspEAICOh6bcYCXS" style="margin-left: 1em; margin-right: 1em;"><img alt="" data-original-height="1080" data-original-width="1920" height="225" src="https://blogger.googleusercontent.com/img/a/AVvXsEjbqrXKka1SWJADLrxney7C8AI7g-YnwLj65Ws1YWN8F38ncJGAJeu_PJY9CPpESFywhn8nrJZyrr_hYaHZg9SKXlw4MoRmb4G34PCq1C8DlkrNiq4ujdqNarb7vX_EXN8sRql5BYjH9KgaJrB-KygFe5E7E7Q1KC4mgh85D3WfsJkKVspEAICOh6bcYCXS" width="400" /></a></div><div class="separator" style="clear: both; text-align: center;"><br /></div><div class="separator" style="clear: both; text-align: center;"><br /></div><a href="https://www.youtube.com/watch?v=IQxTvjjnb7g" style="text-align: left;" target="_blank"><span style="font-size: large;">Click Here for Video Tutorial - VHDL - Language for Hardware Design : Know why you need to learn VHDL?</span></a><br /><br /></div></div></div></div><br /><p></p><p><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;">What is VHDL?
VHDL, short for Very High-Speed Integrated Circuit Hardware Description Language, is a powerful and widely used language for designing digital circuits and systems. If you're interested in digital electronics or pursuing a career in hardware design, learning VHDL is essential.
Why Learn VHDL?
Understanding VHDL gives you the ability to design and simulate complex digital systems, ranging from simple logic gates to advanced processors. VHDL allows you to describe the behavior and structure of these circuits accurately, enabling efficient development and debugging. By learning VHDL, you gain the skills to create efficient and reliable hardware designs.
How to Learn VHDL?
Learning VHDL doesn't have to be intimidating! In this tutorial video, we will guide you through the basics of VHDL, explaining the syntax, data types, and essential concepts. We'll also provide practical examples and hands-on exercises to reinforce your understanding. Whether you're a beginner or have some experience with digital design, this video will help you grasp VHDL quickly.
Join Our VHDL Community
Connect with fellow VHDL enthusiasts and learners in our vibrant community. Share ideas, ask questions, and collaborate with others passionate about hardware design. Our community is a supportive and engaging space to expand your knowledge and stay updated with the latest VHDL developments.
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Subscribe to our community for more informative videos and guidance. Stay tuned for tutorials, tips, and tricks to enhance your skills. Hit the notification bell to never miss an update.</span></p><p><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;"><br /></span></p><p><span style="background-color: white; font-size: 15px; white-space-collapse: preserve;"><span face="Roboto, Noto, sans-serif" style="color: #0d0d0d;"><a href="https://www.youtube.com/watch?v=IQxTvjjnb7g">https://www.youtube.com/watch?v=IQxTvjjnb7g</a></span></span></p><p><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;"><br /></span></p><p><span style="background-color: white; font-size: 15px; white-space-collapse: preserve;"><span face="Roboto, Noto, sans-serif" style="color: #0d0d0d;"><a href="https://www.youtube.com/@Learnandgrowcommunity">https://www.youtube.com/@Learnandgrowcommunity</a>
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</span></span></p><div><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;"><br /></span></div><p><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;"><br /></span></p><p><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;"><br /></span></p><p><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; white-space-collapse: preserve;"><br /></span></p>Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com0tag:blogger.com,1999:blog-8218552835565709409.post-39025492075532097052014-04-11T13:27:00.004+05:302014-04-11T13:31:37.532+05:30 Video Learning Series : Interfacing LED & Switch ::: Task - 3 with Codes & Video<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="font-size: large;"><span style="background-color: #fce5cd;"><u><b><br /></b></u></span></span>
<span style="font-size: large;"><span style="background-color: #fce5cd;"><u><b> Video Learning Series : Interfacing LED & Switch ::: Task - 3</b></u></span></span><br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://www.youtube.com/watch?v=P5hYdB_n6xo&list=UU91Msf7ixvSGlnx_RsKTd7Q" style="margin-left: auto; margin-right: auto;" target="_blank"><img alt="https://www.youtube.com/watch?v=P5hYdB_n6xo&list=UU91Msf7ixvSGlnx_RsKTd7Q" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjmrR98zmKi__ef1epnnV_kOXtAR2rWqSmZ4CNpaDC64k7E62ZlEn3p1vVKpTr52Ae8jYrWLZv-411kjj-2xGgk39nmGAQPH7JlbjHDBIB4siqS1Dntz5_bHIQIX156GyAeOHXXwQULwc6N/s1600/vlcsnap-2014-04-11-13h23m59s251.png" height="225" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><a href="https://www.youtube.com/watch?v=P5hYdB_n6xo&list=UU91Msf7ixvSGlnx_RsKTd7Q" target="_blank">Click Here For Video ::: Video Learning Series (vhdlbynaresh.blogspot.com)</a></td></tr>
</tbody></table>
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Video Link -<br />
<a href="https://www.youtube.com/watch?v=P5hYdB_n6xo&list=UU91Msf7ixvSGlnx_RsKTd7Q">https://www.youtube.com/watch?v=P5hYdB_n6xo&list=UU91Msf7ixvSGlnx_RsKTd7Q</a><br />
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<u><b><span style="background-color: #fce5cd;">TASK 3 :::: </span> </b></u> Interfacing LED & Switch With Cyclone II FPGA Device. -<br />
Description - LED's Starts Blinking when Switch is pressed
& Remains same as it's last update when Switch is released.<br />
In our video we take 8 LED's as output packed in 7- segment package.<br />
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<span style="background-color: #fce5cd;"><u><b>VHDL Code -</b></u></span><br />
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library ieee;<br />
use ieee.std_logic_1164.all;<br />
use ieee.std_logic_arith.all;<br />
use ieee.std_logic_unsigned.all;<br />
<br />
entity sl3 is<br />
port (clk : in std_logic;<br />
din : in std_logic;<br />
dout : out std_logic_vector (7 downto 0));<br />
end sl3;<br />
<br />
architecture sl2_arc of sl3 is<br />
begin<br />
p0 : process (clk,din) is<br />
variable m : std_logic_vector (24 downto 0) := (others=>'0');<br />
begin<br />
if (rising_edge (clk)) then<br />
m := m + 1;<br />
end if;<br />
if (din='0') then<br />
case m(24) is<br />
when '0' => dout <= "00000000";<br />
when others => dout <= "11111111";<br />
end case;<br />
end if;<br />
end process p0;<br />
<br />
end sl2_arc;<br />
<br />
<br />
<br />
<br />
<b>Please revert with your suggestions, likes and comments to make this video series successful and helpful to others.</b><br />
<br />
<span style="font-family: Arial,Helvetica,sans-serif;"><b>I would love to read your suggestions and comments here below</b></span>
<br />
<br />
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>Best Regard //</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>Naresh Singh Dobal</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>nsdobal@gmail.com</b></span></div>
<br />
<br />
<br />
<br />
<br /></div>
Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com1tag:blogger.com,1999:blog-8218552835565709409.post-58984606808853797892014-04-11T13:20:00.001+05:302014-04-11T13:20:25.165+05:30 Video Learning Series : Interfacing LED & Switch ::: Task - 2 with Codes & Video <div dir="ltr" style="text-align: left;" trbidi="on">
<br />
<br />
<br />
<br />
<span style="background-color: #fff2cc;"><u><b><span style="font-size: large;"><br /></span></b></u></span>
<span style="background-color: #fff2cc;"><u><b><span style="font-size: large;"> Video Learning Series : Interfacing LED & Switch ::: Task - 2</span></b></u></span><br />
<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://www.youtube.com/watch?v=rmpQ8F0dziY&list=UU91Msf7ixvSGlnx_RsKTd7Q" style="margin-left: auto; margin-right: auto;" target="_blank"><img alt="https://www.youtube.com/watch?v=rmpQ8F0dziY&list=UU91Msf7ixvSGlnx_RsKTd7Q" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjKeXNQx63spaFFGaj99VCUTCEmIVgXmzOAhAxqaQBiP7BN7dFGb0imLwn2cC7smkWDaMDe3No06nqmA6thKgMc_eTEc_Hh9hNrZDChBgVolZTmYM3_gOVI7TqhUAYTAhKTzMGOG2Ey-9Xm/s1600/vlcsnap-2014-04-11-13h12m19s164.png" height="225" width="400" /> </a></td><td style="text-align: center;"> </td><td style="text-align: center;"> </td></tr>
<tr><td class="tr-caption" style="text-align: center;"><a href="https://www.youtube.com/watch?v=rmpQ8F0dziY&list=UU91Msf7ixvSGlnx_RsKTd7Q" target="_blank">Click Here For Video ::: Video Learning Series (vhdlbynaresh.blogspot.com)</a></td></tr>
</tbody></table>
<br />
<br />
<br />
Video Link -<br />
<a href="https://www.youtube.com/watch?v=rmpQ8F0dziY&list=UU91Msf7ixvSGlnx_RsKTd7Q">https://www.youtube.com/watch?v=rmpQ8F0dziY&list=UU91Msf7ixvSGlnx_RsKTd7Q</a><br />
<br />
<br />
TASK 2 :::: Interfacing LED & Switch With Cyclone II FPGA Device. -<br />
Description - LED's Starts Blinking when Switch is pressed
& goes OFF when Switch is released.<br />
In our video we take 8 LED's as output packed in 7- segment package.<br />
<br />
<br />
<span style="background-color: #fce5cd;"><u><b>VHDL Code -</b></u></span><br />
<br />
<br />
<br />
library ieee;<br />use ieee.std_logic_1164.all;<br />use ieee.std_logic_arith.all;<br />use ieee.std_logic_unsigned.all;<br /><br />entity sl2 is<br />port (clk : in std_logic;<br />din : in std_logic;<br />dout : out std_logic_vector (7 downto 0));<br />end sl2;<br /><br />architecture sl2_arc of sl2 is --frequncy is 50 MHz<br />begin<br /> p0 : process (clk,din) is<br /> variable m : std_logic_vector (24 downto 0) := (others=>'0');<br /> begin<br /> if (rising_edge (clk)) then<br /> m := m + 1;<br /> end if;<br /> if (din='0') then<br /> case m(24) is<br /> when '0' => dout <= "00000000";<br /> when others => dout <= "11111111";<br /> end case;<br /> else<br /> dout <= (others => '0');<br /> end if;<br /> end process p0;<br /> <br />end sl2_arc;<br />
<br />
<br />
<b>Please revert with your suggestions, likes and comments to make this video series successful and helpful to others.</b><br />
<br />
<span style="font-family: Arial,Helvetica,sans-serif;"><b>I would love to read your suggestions and comments here below</b></span>
<br />
<br />
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>Best Regard //</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>Naresh Singh Dobal</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>nsdobal@gmail.com</b></span></div>
</div>
Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com0tag:blogger.com,1999:blog-8218552835565709409.post-31986229678298699532014-04-11T13:04:00.001+05:302014-04-11T13:04:55.201+05:30Video Learning Series : Interfacing LED & Switch ::: Task - 1 with Codes & Video<div dir="ltr" style="text-align: left;" trbidi="on">
<br />
<br />
<br />
<br />
<br />
<span style="background-color: #fce5cd;"><span style="font-size: large;"><u><b>Video Learning Series : Interfacing LED & Switch ::: Task - 1 </b></u></span></span><br />
<br />
<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://www.youtube.com/watch?v=Ea_N3f_JQMc&list=UU91Msf7ixvSGlnx_RsKTd7Q" style="margin-left: auto; margin-right: auto;" target="_blank"><img alt="https://www.youtube.com/watch?v=Ea_N3f_JQMc&list=UU91Msf7ixvSGlnx_RsKTd7Q" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEikAcDI9fNkG5yAioXlr3palUv2lF9s215HBjm5l4dGPi6wGZr2wRTw3gz_OUKZfeIYzfkd21LPER-fWgKorRaBm9y-kZP9w0Cmzk4l_KLj_xAclt9_-D3YutPfInGLHhqJtjaSZlzrjP-g/s1600/vlcsnap-2014-04-11-12h49m10s54.png" height="225" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Click Here For Video ::: Video Learning Series (vhdlbynaresh.blogspot.com)</td></tr>
</tbody></table>
<br />
<br />
<b>Video Link - </b><br />
<a href="https://www.youtube.com/watch?v=Ea_N3f_JQMc&list=UU91Msf7ixvSGlnx_RsKTd7Q">https://www.youtube.com/watch?v=Ea_N3f_JQMc&list=UU91Msf7ixvSGlnx_RsKTd7Q</a><br />
<br />
<br />
TASK 1 :::: Interfacing LED & Switch With Cyclone II FPGA Device. - <br />
Description - LED goes ON when Logic 1 is given by switch as input & goes OFF when Logic '0' is given by switch as input.<br />
In our video we take 8 LED's as output packed in 7- segment package.<br />
<br />
<br />
<span style="background-color: #fce5cd;"><u><b>VHDL Code - </b></u></span><br />
<br />
library ieee;<br />use ieee.std_logic_1164.all;<br /><br />entity sl1 is<br />port (din : in std_logic ;<br />dout : out std_logic_vector (7 downto 0));<br />end sl1;<br /><br />architecture sl1_arc of sl1 is<br />begin<br /><br />dout <= "00000000" when din='0' else<br />"11111111";<br /><br />end sl1_arc;<br />
<br />
<br />
<br />
<b>Please revert with your suggestions, likes and comments to make this video series successful and helpful to others.</b><br />
<br />
<span style="font-family: Arial,Helvetica,sans-serif;"><b>I would love to read your suggestions and comments here below</b></span>
<br />
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>Best Regard //</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>Naresh Singh Dobal</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>nsdobal@gmail.com</b></span></div>
</div>
Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com0tag:blogger.com,1999:blog-8218552835565709409.post-4941213807570655872013-11-19T16:17:00.003+05:302013-11-19T16:18:47.714+05:30VHDL Lab Exercises...<div dir="ltr" style="text-align: left;" trbidi="on">
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<br />
<br />
<div style="text-align: center;">
<span style="font-size: large;"><b><u style="background-color: #fce5cd;">VHDL Lab Exercise...</u></b></span></div>
<div style="text-align: center;">
<span style="font-size: large;"><b><u style="background-color: #fce5cd;"><br /></u></b></span></div>
<div style="text-align: center;">
<b><span style="font-family: Courier New, Courier, monospace;">Learn VHDL with Naresh Singh Dobal Test Series...</span></b></div>
<br />
<br />
<br />
<a href="http://vhdlbynaresh.blogspot.fi/2013/11/vhdl-lab-exercise-exercise-1.html" target="_blank"><b><u>1. LAB Exercise 1</u></b> (Combinational System Design using Gates).</a><br />
<br />
<a href="http://vhdlbynaresh.blogspot.fi/2013/11/vhdl-lab-exercise-exercise-2.html" target="_blank"><u><b>2. LAB Exercise 2</b> </u> (Combinational System Design data flow).</a><br />
<br />
<a href="http://vhdlbynaresh.blogspot.fi/2013/11/vhdl-lab-excercise-exercise-3.html" target="_blank"><u><b>3. LAB Exercise 3</b> </u> (Combinational System Design using Behavior Model).</a><br />
<br />
<a href="http://vhdlbynaresh.blogspot.fi/2013/11/vhdl-lab-exercise-exercise-4.html" target="_blank"><b><u>4. LAB Exercise 4</u></b> (Flip Flop & Latches Design using Behavior Model).</a><br />
<br />
<a href="http://vhdlbynaresh.blogspot.fi/2013/11/vhdl-lab-exercise-exercise-5-lab5.html" target="_blank"><b><u>5. LAB Exercise 5 </u></b> (Counters & Frequency Dividers Design using Behavior Model).</a><br />
<br />
<a href="http://vhdlbynaresh.blogspot.fi/2013/11/vhdl-lab-exercise-exercise-6.html" target="_blank"><b><u>6. LAB Exercise 6</u></b> (Hardware Peripherals & System Design using Behavior Model).</a><br />
<br />
<a href="http://vhdlbynaresh.blogspot.fi/2013/11/vhdl-lab-exercise-exercise-7.html" target="_blank"><b><u>7. LAB Exercise 7 </u></b> (Combinational System Design using Structural Model).</a><br />
<br />
<a href="http://vhdlbynaresh.blogspot.fi/2013/11/vhdl-lab-exercise-exercise-8.html" target="_blank"><b><u>8. LAB Exercise 8 </u></b> (Flip Flop & Shift register design using Structural Model)</a>.<br />
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<br />
<b><u style="background-color: #fce5cd;">I also linked Solutions for most of the assignment</u></b><br />
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>If you feel any difficulties in any assignment then you can follow the links mentioned in the last of assignment pages...</b></span></div>
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<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>I would love to read your suggestions and comments here below.</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
</div>
Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com2tag:blogger.com,1999:blog-8218552835565709409.post-87867055812751585792013-11-19T16:01:00.004+05:302013-11-19T16:01:54.905+05:30VHDL Lab Exercise ::: Exercise 8<div dir="ltr" style="text-align: left;" trbidi="on">
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd;"><span style="font-size: medium;">VHDL Lab Exercise<span style="width: auto;"></span> ::: Exercise 8</span></span></u></b></div>
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd;"><span style="font-size: medium;"><br /></span></span></u></b></div>
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<b><u>LAB- 8 DESIGN OF SHIFT
REGISTERS AND FLIP-FLOPS USING STRUCTURAL MODEL.<o:p></o:p></u></b></div>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjOjUl22UrRahcxYF-bsdRnZezju1W4hwnOKW9xhaYMM1q-MIYFysufLXYNt58MyTcCE6eJVmFipdQFT10M_kqORgHmH1Xge6vGYDhCqOhFKN1fDxaVcUh07QzS_QbfqLBLOLQ2fdnWhE1X/s1600/img11-19-2013-3.59.21+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjOjUl22UrRahcxYF-bsdRnZezju1W4hwnOKW9xhaYMM1q-MIYFysufLXYNt58MyTcCE6eJVmFipdQFT10M_kqORgHmH1Xge6vGYDhCqOhFKN1fDxaVcUh07QzS_QbfqLBLOLQ2fdnWhE1X/s1600/img11-19-2013-3.59.21+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">VHDL Lab Exercise 8 :: VHDL with Naresh Singh Dobal Learning Series.</td></tr>
</tbody></table>
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<b><u><br /></u></b></div>
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<b><u><br /></u></b></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>If you feel any difficulties in any assignment then follow the below link...</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><a href="http://vhdlbynaresh.blogspot.in/2013/07/small-description-about-structural.html" style="color: #3366cc; outline: none;" target="_blank">Solutions for problems in System Design.</a></b></span></div>
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<br /></div>
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<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>I would love to read your suggestions and comments here below.</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
</div>
Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com0tag:blogger.com,1999:blog-8218552835565709409.post-8440674721619738262013-11-19T15:59:00.000+05:302013-11-19T15:59:01.308+05:30VHDL Lab Exercise ::: Exercise 7<div dir="ltr" style="text-align: left;" trbidi="on">
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<b style="color: #222222; font-family: Arial, Verdana; line-height: 20px;"><u><span style="background-color: #fce5cd;"><span style="font-size: large;">VHDL Lab Exercise<span style="width: auto;"></span> ::: Exercise 7</span></span></u></b></div>
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd;"><span style="font-size: x-small;"><br /></span></span></u></b></div>
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd;"><span style="font-size: x-small;"><br /></span></span></u></b></div>
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<b><u><span style="font-family: Courier New, Courier, monospace;">LAB5 COMBINATIONAL SYSTEM
DESIGN USING STRUCTURAL MODEL.</span><o:p></o:p></u></b></div>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgEGtEGo3IV_aR8nMW1DnPPnNGs_TqSO1rZwBNTOZLHffgOCvNHjQ4gJeTlFw4TudZfPIdy3iGQJz1bEKY0y7a48wSTEDetY1VPOcgRnNybS5xEIFaXpR5AOt-pO22zxD07SqjEXRLJK9vr/s1600/img11-19-2013-3.56.26+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgEGtEGo3IV_aR8nMW1DnPPnNGs_TqSO1rZwBNTOZLHffgOCvNHjQ4gJeTlFw4TudZfPIdy3iGQJz1bEKY0y7a48wSTEDetY1VPOcgRnNybS5xEIFaXpR5AOt-pO22zxD07SqjEXRLJK9vr/s1600/img11-19-2013-3.56.26+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">VHDL Lab Exercise 7 :: VHDL with Naresh Singh Dobal Learning Series.</td></tr>
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<b><u><span style="font-family: Courier New, Courier, monospace;"><br /></span></u></b></div>
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<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>If you feel any difficulties in any assignment then follow the below link...</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><a href="http://vhdlbynaresh.blogspot.in/2013/07/small-description-about-structural.html" target="_blank">Solutions for problems in System Design.</a></b></span></div>
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<br /></div>
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<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>I would love to read your suggestions and comments here below.</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
</div>
Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com0tag:blogger.com,1999:blog-8218552835565709409.post-11275039050689909502013-11-19T15:19:00.003+05:302013-11-19T15:19:45.164+05:30VHDL Lab Exercise ::: Exercise 6<div dir="ltr" style="text-align: left;" trbidi="on">
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd;"><span style="font-size: small;">VHDL Lab Exercise<span style="width: auto;"></span> ::: Exercise 6</span></span></u></b></div>
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd;"><span style="font-size: small;"><br /></span></span></u></b></div>
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<b><u>LAB 6 : HARDWARE PERIPHERALS & SYSTEM DESIGNS.<o:p></o:p></u></b></div>
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd;"><span style="font-size: small;"><br /></span></span></u></b></div>
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd;"><span style="font-size: small;"><br /></span></span></u></b></div>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEitepQdiVcYcSX8pRQcKBVy-0jy8UbThSVZGObFn3V9tXmt5_uzc1AwNcf1-AC0-xqiqEw10-iCLYgQP1zwXNC48sTERTTBaf0pyeR-nXiHTzx5LKOXv8IYytB_jaOopcb3fxTZhu7cwNI8/s1600/img11-19-2013-3.16.25+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEitepQdiVcYcSX8pRQcKBVy-0jy8UbThSVZGObFn3V9tXmt5_uzc1AwNcf1-AC0-xqiqEw10-iCLYgQP1zwXNC48sTERTTBaf0pyeR-nXiHTzx5LKOXv8IYytB_jaOopcb3fxTZhu7cwNI8/s1600/img11-19-2013-3.16.25+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Lab Exercise 6 :: VHDL with Naresh Singh Dobal Learning Series.</td></tr>
</tbody></table>
<div style="text-align: center;">
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd;"><span style="font-size: small;"><br /></span></span></u></b></div>
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd;"><span style="font-size: small;"><br /></span></span></u></b></div>
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd;"><span style="font-size: small;"><br /></span></span></u></b></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>If you feel any difficulties in any assignment then follow the below link...</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><a href="http://vhdlbynaresh.blogspot.in/2013/07/sample-programs-for-basic-systems-using.html" target="_blank">Solutions for problems System Design.</a></b></span></div>
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<br /></div>
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<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>I would love to read your suggestions and comments here below.</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com</b></span></div>
</div>
Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com0tag:blogger.com,1999:blog-8218552835565709409.post-44962991721675442472013-11-19T14:51:00.003+05:302013-11-19T15:06:36.179+05:30VHDL Lab Exercise ::: Exercise 5<div dir="ltr" style="text-align: left;" trbidi="on">
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<b style="color: #222222; font-family: Arial, Verdana; line-height: 20px;"><u><span style="background-color: #fce5cd;"><span style="font-size: medium;">VHDL Lab Exercise<span style="width: auto;"></span> ::: Exercise 5</span></span></u></b></div>
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<b style="color: #222222; font-family: Arial, Verdana; line-height: 20px;"><u><span style="background-color: #fce5cd;"><span style="font-size: medium;"><br /></span></span></u></b></div>
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<b><u>LAB5 : COUNTERS AND FREQUENCY DIVIDERS.<o:p></o:p></u></b></div>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiTdQRkwP1o7524VyjNoz5GYFcFLQhNgVb0JVch82iiTlSJq6mdHo8xr5bfScH6b3RqZ4KrF3fAz6Pe_esVX5WoR6C14YzDk0SUC7BhtfNPGaAEyIE5APBCKuqpTnzUek-brR7m6DmNp4Wi/s1600/img11-19-2013-2.47.30+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiTdQRkwP1o7524VyjNoz5GYFcFLQhNgVb0JVch82iiTlSJq6mdHo8xr5bfScH6b3RqZ4KrF3fAz6Pe_esVX5WoR6C14YzDk0SUC7BhtfNPGaAEyIE5APBCKuqpTnzUek-brR7m6DmNp4Wi/s1600/img11-19-2013-2.47.30+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Lab Exercise 5 : VHDL with Naresh Singh Dobal Learning Series.</td></tr>
</tbody></table>
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<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>If you feel any difficulties in any assignment then follow the below link...</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><a href="http://vhdlbynaresh.blogspot.in/2013/07/counters-design-in-vhdl.html" target="_blank"><span style="color: #3366cc;">Solutions for problems C</span>ounter Design.</a></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><a href="http://vhdlbynaresh.blogspot.in/2013/07/design-of-frequency-dividers-in-vhdl.html" target="_blank"><span style="color: #3366cc;">Solution for problems in </span>Frequency Divider Design.</a></b></span></div>
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<br /></div>
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<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>I would love to read your suggestions and comments here below.</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com</b></span></div>
</div>
Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com0tag:blogger.com,1999:blog-8218552835565709409.post-14314443198416486342013-11-19T13:54:00.003+05:302013-11-19T14:55:47.850+05:30VHDL Lab Exercise ::: Exercise 4<div dir="ltr" style="text-align: left;" trbidi="on">
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<b style="color: #222222; font-family: Arial, Verdana; line-height: 20px;"><u><span style="background-color: #fce5cd;"><span style="font-size: large;">VHDL Lab Exercise ::: Exercise 4 -</span></span></u></b></div>
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd; font-size: x-small;"><br /></span></u></b></div>
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd; font-size: x-small;"><br /></span></u></b></div>
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<u><b><span style="font-family: Courier New, Courier, monospace; font-size: large;">LAB4 : LATCHES & FLIP-FLOPS & ALU.</span><o:p></o:p></b></u></div>
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd; font-size: x-small;"><br /></span></u></b></div>
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd; font-size: x-small;"><br /></span></u></b></div>
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd; font-size: x-small;"><br /></span></u></b></div>
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEitPKMNPH13ELTqTfDKVDRy127zWkdKIm1NzS6OOaa_zoBr0YSpnv1KwvBaG-AhKr2P37tWWkAqeN8jCLgBwQt5MGEwet5_GGCe_qYx16C4vI0Sn8ycXkZDgPKsDBVQBwzzHs4hXbwWYldV/s1600/img11-19-2013-2.52.51+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEitPKMNPH13ELTqTfDKVDRy127zWkdKIm1NzS6OOaa_zoBr0YSpnv1KwvBaG-AhKr2P37tWWkAqeN8jCLgBwQt5MGEwet5_GGCe_qYx16C4vI0Sn8ycXkZDgPKsDBVQBwzzHs4hXbwWYldV/s1600/img11-19-2013-2.52.51+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Lab Exercise 4 : VHDL with Naresh Singh Dobal Learning Series.</td></tr>
</tbody></table>
<br /></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;"><br /></span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;"><br /></span></b></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>If you feel any difficulties in any assignment then follow the below link...</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><a href="http://vhdlbynaresh.blogspot.in/2013/07/how-to-use-if-else-statements-in.html" style="color: #3366cc; outline: none; text-decoration: none;" target="_blank">Solutions for problems in if-else statements.</a></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><a href="http://vhdlbynaresh.blogspot.in/2013/07/how-to-use-case-statements-in-behavior.html" style="color: #3366cc; outline: none; text-decoration: none;" target="_blank">Solution for problems in case statements.</a></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<br /></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>I would love to read your suggestions and comments here below.</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com</b></span></div>
</div>
Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com7tag:blogger.com,1999:blog-8218552835565709409.post-8976263633575580122013-11-19T13:42:00.004+05:302013-11-19T15:00:39.861+05:30VHDL Lab Excercise ::: Exercise 3<div dir="ltr" style="text-align: left;" trbidi="on">
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<br />
<br />
<br />
<br />
<div style="text-align: center;">
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd; font-size: small;">VHDL Lab Exercise ::: Exercise 3 -</span></u></b></div>
<div align="center" class="MsoNormal" style="text-align: center;">
<b><u><br /></u></b></div>
<div align="center" class="MsoNormal" style="text-align: center;">
<b><u>LAB 3 : COMBINATIONAL SYSTEM DESIGN USING BEHAVIOR MODELLING STYLE.<o:p></o:p></u></b></div>
<div align="center" class="MsoNormal" style="text-align: center;">
<b><u><br /></u></b></div>
<div align="center" class="MsoNormal" style="text-align: center;">
<b><u><br /></u></b>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi8K6aLNy3FYJbzRrIvefGj78cLxWSHPegh5kyHyqIotDlC-BiMEYfTArNqay6NNBKOOOoJRmk_38EJGdTfLQxsUBoZMKuJDQm1LArg7pzMIMo2_VjSjddXsNpZ2uxOHj2yqqqgfzKPiouT/s1600/img11-19-2013-2.56.47+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi8K6aLNy3FYJbzRrIvefGj78cLxWSHPegh5kyHyqIotDlC-BiMEYfTArNqay6NNBKOOOoJRmk_38EJGdTfLQxsUBoZMKuJDQm1LArg7pzMIMo2_VjSjddXsNpZ2uxOHj2yqqqgfzKPiouT/s1600/img11-19-2013-2.56.47+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Lab Exercise 3 : VHDL with Naresh Singh Dobal Learning Series.</td></tr>
</tbody></table>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh9pfONuHpY-Rq_JAA0QpFZv0kwE9l5TolmfgoHO7kN7XyZfbGBy83kC34QiL6cV7C4qhy6vQdoWwi6pCIooefDqBfGUEwMnEJiOu6TeR8_au2LJ5_uTOUqkqJOQwYTpcwCf1bxSETTINiR/s1600/img11-19-2013-2.59.27+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh9pfONuHpY-Rq_JAA0QpFZv0kwE9l5TolmfgoHO7kN7XyZfbGBy83kC34QiL6cV7C4qhy6vQdoWwi6pCIooefDqBfGUEwMnEJiOu6TeR8_au2LJ5_uTOUqkqJOQwYTpcwCf1bxSETTINiR/s1600/img11-19-2013-2.59.27+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Lab Exercise 3-b :: VHDL with Naresh Singh Dobal Learning Series.</td></tr>
</tbody></table>
<b><u><br /></u></b></div>
<div style="text-align: justify;">
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd; font-size: small;"><br /></span></u></b></div>
<div class="Section1">
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task1 : Write a VHDL code for Full adder using if-else.</span></b></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;">Task2: Write
a VHDL code for Full subtractor using if-else.</span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task3: Write a VHDL code for 4:1 Multiplexer using if-else.</span></b></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;">Task4: Write a VHDL code for 1:4 Demultiplexer using if-else.</span></b></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;">Task5: Write a VHDL code for a 8:3 Encoder using if-else. </span></b></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;">Task6: Write a VHDL code for a 3:8 Decoder using if-else. </span></b></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;">Task7: Write a VHDL code for Full adder using case. </span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task8 : Write a VHDL code for Full subtractor using case. </span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task9: Write
a VHDL code for 4:1 Multiplexer using case. </span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task10: Write a VHDL code for 1:4 Demultiplexer using case. </span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task11: Write a VHDL code for 8:3 Encoder using case. </span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task12: Write a VHDL code for 3:8 Decoder using case. </span></b></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;">Task13: Write a VHDL code for 3 bit comparator using if-else. </span></b></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;">Task14: Write a VHDL code for BINARY TO GRAY converter using if-else. </span></b></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;">Task15: Write a VHDL code for GRAY TO BINARY converter using case.</span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;"><br /></span></b></div>
</div>
<div align="center">
<br /></div>
<div style="text-align: justify;">
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px; text-align: left;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>If you feel any difficulties in any assignment then follow the below link...</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px; text-align: left;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px; text-align: left;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><a href="http://vhdlbynaresh.blogspot.in/2013/07/how-to-use-if-else-statements-in.html" target="_blank">Solutions for problems in if-else statements.</a></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px; text-align: left;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><a href="http://vhdlbynaresh.blogspot.in/2013/07/how-to-use-case-statements-in-behavior.html" target="_blank">Solution for problems in case statements.</a></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px; text-align: left;">
<br /></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px; text-align: left;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px; text-align: left;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>I would love to read your suggestions and comments here below.</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px; text-align: left;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com</b></span></div>
</div>
<div align="center">
<br /></div>
</div>
Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com0tag:blogger.com,1999:blog-8218552835565709409.post-30977979214495946722013-11-19T13:14:00.002+05:302013-11-19T15:03:13.233+05:30VHDL Lab Exercise ::: Exercise 2<div dir="ltr" style="text-align: left;" trbidi="on">
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<br />
<br />
<br />
<div style="text-align: right;">
<br /></div>
<div style="text-align: center;">
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd; font-size: medium;">VHDL Lab Exercise ::: Exercise 2 -</span></u></b></div>
<div style="text-align: center;">
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><u><span style="background-color: #fce5cd; font-size: medium;"><br /></span></u></b></div>
<div align="center" class="MsoNormal" style="text-align: center;">
<b><u>LAB2 : COMBINATIONAL SYSTEM DESIGN USING DATA FLOW MODELLING STYLE.<o:p></o:p></u></b></div>
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px; text-align: center;"><u><span style="background-color: #fce5cd; font-size: medium;"><br /></span></u></b>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhe_hwx9ebDwu4zemAhqctPcVzC95G355eorguZaUszdkUZcohkC6zKdQ_teZYUY4raM-7MKgXhpTluyHwOMYkrO14fe_u6lMojjfOZgdXYW-Kk2uV7zkaSaLIW86QZ-EflHUXrr3sVDUWd/s1600/img11-19-2013-3.01.09+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhe_hwx9ebDwu4zemAhqctPcVzC95G355eorguZaUszdkUZcohkC6zKdQ_teZYUY4raM-7MKgXhpTluyHwOMYkrO14fe_u6lMojjfOZgdXYW-Kk2uV7zkaSaLIW86QZ-EflHUXrr3sVDUWd/s1600/img11-19-2013-3.01.09+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Lab Exercise 2a :: VHDL with Naresh Singh Dobal Learning Series.</td></tr>
</tbody></table>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj9hYBf0coOPMx66-8lUVew8gTpodQSmgkNdEQMsAXkwdWlBOm7VNWeLa7q0vcOiLuEWS3wOckUyWkEtJhzQXGuU4CkMeTBpVcjDMnalx8J_dbAWHUCi8lUakZJQA_CG7iCr-tVcWZTsAsF/s1600/img11-19-2013-3.02.19+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj9hYBf0coOPMx66-8lUVew8gTpodQSmgkNdEQMsAXkwdWlBOm7VNWeLa7q0vcOiLuEWS3wOckUyWkEtJhzQXGuU4CkMeTBpVcjDMnalx8J_dbAWHUCi8lUakZJQA_CG7iCr-tVcWZTsAsF/s1600/img11-19-2013-3.02.19+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Lab Exercise 2-b :: VHDL with Naresh Singh Dobal Learning Series.</td></tr>
</tbody></table>
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px; text-align: center;"><u><span style="background-color: #fce5cd; font-size: medium;"><br /></span></u></b>
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px; text-align: center;"><u><span style="background-color: #fce5cd; font-size: medium;"><br /></span></u></b>
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px; text-align: center;"><u><span style="background-color: #fce5cd; font-size: medium;"><br /></span></u></b>
<br />
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task1 : Write a VHDL code for all gates using with-select. </b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task2: Write
a VHDL code for Full adder using with-select.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task3: Write a VHDL code for Full subtractor using with-select. .</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task4: Write a VHDL code for 4:1 Multiplexer using With-select.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task5: Write a VHDL code for a 1:4 Demultiplexer using with-select.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task6: Write a VHDL code for a 8:3 Encoder using With-Select.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task7: Write a VHDL code for a 3:8 Decoder using With-Select.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task8 : Write a VHDL code for all gates using when-else.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task9: Write
a VHDL code for Full adder using when-else.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task10: Write a VHDL code for Full subtractor using when-else.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task11: Write a VHDL code for 4:1 Multiplexer using When-else. .</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task12: Write a VHDL code for a 1:4 Demultiplexer using when-else.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task13: Write a VHDL code for a 8:3 Encoder using When-else.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task14: Write a VHDL code for a 3:8 Decoder using When-else.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task15: Write a VHDL code for 8:3 Encoder with Priority using when-else.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task16: Write
a VHDL code for BINARY to GRAY Converter using with-select.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task17: Write a VHDL code for GRAY to BINARY Converter using with-select.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task18: Write a VHDL code for BINARY to GRAY Converter using when-else.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task19: Write a VHDL code for GRAY to BINARY Converter using when-else.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task20: Write a VHDL code for BINARY to EXCESS-3 using With-select.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task21: Write a VHDL code for BINARY TO GRAY Converter using equation.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>Task22: Write a VHDL code for GRAY to BINARY Converter using equations.</b></span></div>
<span style="font-size: 11pt; line-height: 115%;"><span style="font-family: Arial, Helvetica, sans-serif;"><b>Task23: Write a VHDL code for BINARY TO EXCESS-3 using
equations.</b></span></span><br />
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px; text-align: center;"><u><span style="background-color: #fce5cd; font-size: medium;"><br /></span></u></b>
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px; text-align: center;"><u><span style="background-color: #fce5cd; font-size: medium;"><br /></span></u></b>
<br />
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>If you feel any difficulties in any assignment then follow the below link...</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><a href="http://vhdlbynaresh.blogspot.in/2013/07/blog-post_14.html" target="_blank"><span style="color: #3366cc;">S</span>olutions for problems in with-select statements.</a></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><a href="http://vhdlbynaresh.blogspot.in/2013/07/blog-post_3090.html" target="_blank">Solution for problems in when-else statements.</a></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<br /></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>I would love to read your suggestions and comments here below.</b></span></div>
<div class="MsoNormal" style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com</b></span></div>
</div>
Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com0tag:blogger.com,1999:blog-8218552835565709409.post-22880794986317866872013-11-19T13:05:00.002+05:302013-11-19T15:04:55.184+05:30VHDL Lab Exercise :: Exercise 1<div dir="ltr" style="text-align: left;" trbidi="on">
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<div style="text-align: center;">
<b><u><span style="background-color: #fce5cd; font-size: large;">VHDL Lab Exercise ::: Exercise 1 -</span></u></b></div>
<div style="text-align: center;">
<br /></div>
<div style="text-align: center;">
<br /></div>
<div style="text-align: center;">
<b><u><span style="font-family: Courier New, Courier, monospace; line-height: 115%;">LAB 1: COMBINATIONAL SYSTEM DESIGN USING BASIC GATES
AND EQUATIONS.</span></u></b></div>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgN20IJ4PyJlT4IziT6GIneB2VVYhLcauvGP-gVymfhMmOW3P5fhtotzxLSKbsoQvihZGg28jgaPW36kR1P316J7SF4Ly_LJXNTIf6I7lI3De7Kfd1GY7LjH4KXQXEsYqVIOIv8snbpWs8b/s1600/img11-19-2013-3.03.51+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgN20IJ4PyJlT4IziT6GIneB2VVYhLcauvGP-gVymfhMmOW3P5fhtotzxLSKbsoQvihZGg28jgaPW36kR1P316J7SF4Ly_LJXNTIf6I7lI3De7Kfd1GY7LjH4KXQXEsYqVIOIv8snbpWs8b/s1600/img11-19-2013-3.03.51+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">VHDL Lab Exercise 1 :: VHDL with Naresh Singh Dobal Learning Series.</td></tr>
</tbody></table>
<b><u><span style="font-family: "Calibri","sans-serif"; font-size: 11.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: Mangal; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: "Times New Roman"; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-fareast; mso-hansi-theme-font: minor-latin;"><br /></span></u></b>
<b><u><span style="font-family: "Calibri","sans-serif"; font-size: 11.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: Mangal; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: "Times New Roman"; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-fareast; mso-hansi-theme-font: minor-latin;"><br /></span></u></b>
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<b><span style="font-family: Arial, Helvetica, sans-serif;">Task1 : Write a VHDL
Program for all Logic Gates.</span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task2 : Write a VHDL
code for a Half Adder using Digital Electronics.</span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task3 : Write a VHDL
code for a Full Adder using Digital Electronics.</span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task4 : Write a VHDL
code for a Half Subtractor using Digital Electronics.</span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task5 : Write a VHDL
code for a Full Subtractor using Digital Electronics.</span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task6: Write a VHDL
code for a 4:1 Multiplexer using Digital Electronics.</span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task7: Write a VHDL
code for a 1:4 Multiplexer using Digital Electronics.</span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task8: Write a VHDL
code for a 4:2 Encoder using Digital Electronics.</span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task9: Write a VHDL
code for a 2:4 Decoder using Digital Electronics.</span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;">Task10: Write a VHDL
code for 1 bit Comparator using Digital Electronics. </span></b></div>
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<b><span style="font-family: Arial, Helvetica, sans-serif;"><br /></span></b></div>
<div class="MsoNormal">
<b><span style="font-family: Arial, Helvetica, sans-serif;"><br /></span></b></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>If you feel any difficulties in any assignment then follow the below link...</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><a href="http://vhdlbynaresh.blogspot.in/2013/07/digital-system-design-using-logical.html" target="_blank">Solutions of assignment paper 1.</a></b></span></div>
<div class="MsoNormal">
<br /></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b><br /></b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>I would love to read your suggestions and comments here below.</b></span></div>
<div class="MsoNormal">
<span style="font-family: Arial, Helvetica, sans-serif;"><b>My name is Naresh Singh Dobal, for any query contact me at nsdobal@gmail.com</b></span></div>
<div class="MsoNormal">
<br /></div>
</div>
Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com0tag:blogger.com,1999:blog-8218552835565709409.post-19114350812156231262013-11-12T16:21:00.001+05:302013-11-12T16:21:54.270+05:30A Small Discussion about VHDL & Verilog HDL...<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="background-color: #fce5cd;"><span style="font-size: large;"><u><b>A Small Discussion about VHDL & Verilog HDL -</b></u></span></span><br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiaWaanVnGH0kM-U-3oAV05hovFh0Or_mtlYzJAbqMcZyLT9gG-XmaV7nNjPOImMMs2dX3RK2H6KIBoWqlUf2uzODrXdxnGPberEGgzoDTHffZbS90w_AOKQsq_15BXF7gMZcFWQ2cxiFNM/s1600/img11-12-2013-4.13.52+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiaWaanVnGH0kM-U-3oAV05hovFh0Or_mtlYzJAbqMcZyLT9gG-XmaV7nNjPOImMMs2dX3RK2H6KIBoWqlUf2uzODrXdxnGPberEGgzoDTHffZbS90w_AOKQsq_15BXF7gMZcFWQ2cxiFNM/s1600/img11-12-2013-4.13.52+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">VHDL or Verilog HDL - A small discussion (VHDL with Naresh Singh Dobal learning Series).</td></tr>
</tbody></table>
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<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>Verilog HDL is easier to understand and use, It is very effectively used for
simulation and synthesis. but it lacks for system level or complex designing.
It is promoted by OVI (Open Verilog International). It is widely used for ASIC
designing or lower level design (RTL or lower), but this results in
faster simulation and effective synthesis. Mostly used in North America, Asia
& Japan, but not popular in Europe.</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>As comparable to verilog HDL, VHDL is more complex, thus difficult to learn
and use. But this offers more flexibility of designing. Since VHDL is better
suited for handling very complex systems, so it is now gaining popularity. VHDL
<span style="mso-spacerun: yes;"> </span>is mainly promoted by VHDL
international. VHDL is relatively weaker in lower designs. But superior in
system level design. Many believes that in long terms presents better condition
and adaptability than its competitors. This language is widely used in Europe,
significantly used in US and Canada, but this disliked in Japan...</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>Both the HDL's are used to describe electronic systems.</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>The function of systems is to get input data from it's environment and give
output some data in return.</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>In verilog HDL this is called a module which is a basic building block in
Verilog HDL, and in VHDL this is defined in Entity & Architecture Pair.</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b> Both the Languages are IEEE Standard.</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b><br />
I would love to read your suggestions and comments here below,</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>Best Regard //</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>Naresh Singh Dobal</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>
</b></span></div>
<div style="text-align: justify;">
<span style="font-family: Arial,Helvetica,sans-serif;"><b>nsdobal@gmail.com</b></span></div>
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Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com1tag:blogger.com,1999:blog-8218552835565709409.post-56191405709317961032013-11-11T14:16:00.010+05:302023-09-02T20:35:37.956+05:30Basics of VHDL Language Execution process concurrent and sequential<div dir="ltr" style="text-align: left;" trbidi="on">
<br /><div style="text-align: center;"><a href="https://youtu.be/6ef5kA8XKLc" target="_blank"><span style="font-size: medium;"><b>Click here for Video Tutorial - <span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; white-space-collapse: preserve;">VHDL Basics : Insights Sequential and Concurrent Statements - No More Confusion [Beginner’s Guide]</span></b></span></a></div>
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<div class="separator" style="clear: both; text-align: center;"><div class="separator" style="clear: both; text-align: center;"><a href="https://youtu.be/6ef5kA8XKLc" style="margin-left: 1em; margin-right: 1em;" target="_blank"><img alt="" data-original-height="978" data-original-width="1744" height="224" src="https://blogger.googleusercontent.com/img/a/AVvXsEhVyTImzFpmtZbXkCeE3p0Y4PSNSk1aOckpswD8nVyV6eJ58fVgWcEF-j_ryw_k3Ime6mf_gxDOw23KZzAxUMqdZdAtuqAhGejw3MwRGm5xuy4zrC9gfhISObx6xiMC3cNe3H-023HQVEc5HyOqe-y_qH6ZC-llz4DbymFZ5_xGjXd0yuL4rS-MnZhren65=w400-h224" width="400" /></a></div><br /><br /></div><span style="background-color: #fff2cc;"><span style="font-size: large;"><u><b><br /></b></u></span></span>
<span style="background-color: #fff2cc;"><span style="font-size: large;"><u><b>Basics of VHDL Execution Process (Concurrent and Sequential) </b></u></span></span><br />
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<span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; text-align: start; white-space-collapse: preserve;">In this comprehensive tutorial, we will cover everything you need to know about VHDL sequential and concurrent statements. Sequential statements allow us to execute code in a step-by-step manner, while concurrent statements offer a more parallel execution approach.
Welcome to this beginner's guide on VHDL basics, where we will dive into the concepts of sequential and concurrent statements in VHDL. If you've ever been confused about these fundamental aspects of VHDL programming, this video is perfect for you.
We will start by explaining the differences between sequential and concurrent statements, providing clear examples and illustrations to eliminate any confusion. By the end of this video, you will have a solid understanding of how to effectively utilize sequential and concurrent statements in your VHDL designs.
This guide is suitable for beginners who have some basic knowledge of VHDL. We will go step-by-step and explain each concept thoroughly, ensuring that you grasp the fundamentals before moving on to more advanced topics.
Make sure to subscribe to our channel for more informative videos on VHDL programming and digital design. Don't forget to hit the notification bell to stay updated with our latest uploads. If you have any questions or suggestions, feel free to leave them in the comments section below.</span></div><div style="text-align: justify;"><span face="Roboto, Noto, sans-serif" style="background-color: white; color: #0d0d0d; font-size: 15px; text-align: start; white-space-collapse: preserve;"><br /></span></div>
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<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; text-align: justify; unicode-bidi: embed; vertical-align: baseline;"><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><span style="mso-spacerun: yes;"><b> </b> </span>Before start writing of codes in VHDL
for digital systems you must know about the execution of VHDL language, you
should know that how the tools process the VHDL code. This is a very important
concept you should understand for proficiency in VHDL.</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
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<span style="background-color: #fce5cd;"><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">VHDL can be programmed in following
execution pattern.</span></span></div>
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<span style="font-size: 12pt;"><span style="mso-special-format: "numbullet3\,1";">1.</span></span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Concurrent Execution.</span></div>
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<span style="font-size: 12pt;"><span style="mso-special-format: "numbullet3\,1";">2.</span></span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Sequential Execution.</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> </span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> </span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
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<span style="background-color: #fce5cd;"><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">VHDL can work on –</span></span></div>
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<span style="font-size: 12pt;"><span style="mso-special-format: "numbullet3\,1";">1.</span></span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Concurrent Statements.</span></div>
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<span style="font-size: 12pt;"><span style="mso-special-format: "numbullet3\,1";">2.</span></span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Sequential Statements.</span></div>
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<span style="font-size: 12pt;"><span style="mso-special-format: "numbullet3\,1";">3.</span></span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Net-List Language.</span></div>
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<div style="direction: ltr; margin-bottom: 0pt; margin-left: 0.25in; margin-top: 4.32pt; text-align: justify; text-indent: -0.25in; unicode-bidi: embed; vertical-align: baseline;">
<span style="font-size: 12pt;"><span style="mso-special-format: "numbullet3\,1";">4.</span></span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Timing Specification.</span></div>
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<span style="font-size: 12pt;"><span style="mso-special-format: "numbullet3\,1";">5.</span></span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Waveform Generation Language.</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> </span></div>
<div style="direction: ltr; margin-bottom: 0pt; margin-left: 0.25in; margin-top: 4.32pt; text-align: justify; text-indent: -0.25in; unicode-bidi: embed; vertical-align: baseline;">
<span style="color: black; font-family: Arial; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><span style="font-size: 12pt;"> </span><div class="separator" style="clear: both; text-align: center;"><div class="separator" style="clear: both; text-align: left;">Sequential statements are very much like software languages. These statements execute sequentially that means at the start statement 1 will execute and then statement 2 will execute than statement 3 will execute and so on.</div><div class="separator" style="clear: both; text-align: left;"><br /></div><div class="separator" style="clear: both; text-align: left;">This means that sequential statements must be in correct order, just like the flow-charts we have in software. Let’s understand this with a simple example.</div></div><br /></span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">If (a=b) then</span></div>
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</span></span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">eq</span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> <= ‘1’;</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Else</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><span style="mso-spacerun: yes;">
</span></span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">eq</span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> <= ‘0’;</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">End if;</span></div>
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<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; unicode-bidi: embed; vertical-align: baseline;">We also have the concurrent statements in VHDL, these statements are very likely to a hardware model like a schematic design. All the concurrent statements execute simultaneously, just like hardware. </div><div><br /></div><div>So if you have Concurrent statement 1 and statement 2 and 3 and 4 and so on… and all these statements executes concurrently, which means when the concurrent statement 1 is executing at the same time statement 4 is executing, similarly at the same time statement 2 or statement 3 are executing. I mean all are executing at the same time, so this is important to know that the sequence or order of the statements not really matter if your statement executing concurrently, and you can write them anywhere within the architecture without thinking of the sequence. And the results will be the same.</div><div><br /></div><div><br /></div></div>
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</span></div>
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<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; text-align: justify; unicode-bidi: embed; vertical-align: baseline;"><span style="font-family: Arial; font-size: medium;"><a href="https://youtu.be/6ef5kA8XKLc" target="_blank"><b>Click here for examples and deep understanding and Video tutorials.</b></a></span></div>
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<span style="background-color: #fff2cc;"><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Net list language –</span></span></div>
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<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; text-align: justify; unicode-bidi: embed; vertical-align: baseline;">
<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Net list language is also working on
Concurrent execution. But only the difference is in net list language we design
our system by defining the basic elements like gates or collection of gates
(called modules and registers). </span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></div>
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</div>
<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; text-align: justify; unicode-bidi: embed; vertical-align: baseline;">
<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">** Above three languages are used for
designing purpose.</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></div>
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<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; text-align: justify; unicode-bidi: embed; vertical-align: baseline;">
<span style="color: black; font-family: Arial; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><span style="font-size: 12pt;">Other two languages i.e. Timing
specification </span>and waveform<span style="font-size: 12pt;"> generation
language are used for verification purpose. In brief-</span></span></div>
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<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; text-align: justify; unicode-bidi: embed; vertical-align: baseline;">
<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><span style="background-color: #fff2cc;"><u>Timing Specification -</u></span><span style="mso-spacerun: yes;"><span style="background-color: #fff2cc;"><u> </u></span> </span>we can define the flow of data from input to
output in our simulation screen but again this cannot be implemented in real
life hardware because you can't specify the time of flow of data. So timing
specification language only use in writing of test benches. Same a waveform
generation language,</span></div>
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<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; text-align: justify; unicode-bidi: embed; vertical-align: baseline;">
<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Is used for creation of waveforms,
basically this is a<span style="mso-spacerun: yes;"> </span>algorithm to get the
same output by minimizing the processing time.</span></div>
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Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com1tag:blogger.com,1999:blog-8218552835565709409.post-59225218972488750792013-11-08T15:35:00.008+05:302023-09-02T20:49:38.845+05:30VHDL/ FPGA Design Flow<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="background-color: #fce5cd;"><span face="Arial,Helvetica,sans-serif"><span style="font-size: large;"><b><u><a href="https://youtu.be/uX37uKdR31A" target="_blank"><span style="color: black; font-weight: normal;"></span><span style="color: black; font-weight: normal; vertical-align: baseline;">VHDL / FPGA </span><span style="color: black; font-weight: normal;">Design Flow –</span></a></u></b></span></span></span></div>
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<a href="https://youtu.be/uX37uKdR31A" target="_blank"><span style="color: black; font-family: Arial; font-size: 12pt;"> </span><span face="Arial, Tahoma, Helvetica, FreeSans, sans-serif" style="background-color: white; color: #2288bb; font-size: medium; text-align: center; text-decoration-line: none;"><b>Click here for Video Tutorial - <span face="Roboto, Noto, sans-serif" style="color: #0d0d0d; white-space-collapse: preserve;">VHDL Basics : Insights Sequential and Concurrent Statements - No More Confusion [Beginner’s Guide]</span></b></span></a></div><div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; unicode-bidi: embed; vertical-align: baseline;"><span style="font-family: Arial;"><br /></span></div><div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; unicode-bidi: embed; vertical-align: baseline;"><span style="font-family: Arial;"><div class="separator" style="clear: both; text-align: center;"><a href="https://youtu.be/uX37uKdR31A" style="margin-left: 1em; margin-right: 1em;" target="_blank"><img alt="" data-original-height="1080" data-original-width="1920" height="225" src="https://blogger.googleusercontent.com/img/a/AVvXsEjfiOErCeA9weefR6lOGp0kIRnjBQAsRyenZBfHQWsNSf9t0viesWTh5Iu572cLKhJjgv7WTpyl8E2-wNKNDvmiCYg9DP_UuEWsr4q5TyW_uMji_8rUJH8U-B41k2VEybU2AkkFT1MtG4AnL4P3FdSrGaEw7WkxMtX9haviS5L6-LxNuqrl6j7L0XtINnw7=w400-h225" width="400" /></a></div><br /><br /></span></div><div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; unicode-bidi: embed; vertical-align: baseline;"><br /></div><div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; unicode-bidi: embed; vertical-align: baseline;">
<br /><table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td><span style="margin-left: auto; margin-right: auto;"><a href="https://youtu.be/uX37uKdR31A" target="_blank"><img border="0" height="304" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhmfi-3ms2OBnLGaWxqjRVzXobN8stEicTtthiYJmMQtHrloRN-fs0yxJ-lJQiOqFw9zP14LlHMFQhpiBa0a9c8tKaZ1KQiqomdY82kmJgKOTRb3hPOOdAB-V1fRoaaUJmpSI39TbvJKqHi/w400-h304/img11-8-2013-3.19.35+PM.jpg" width="400" /></a></span></td></tr>
<tr><td class="tr-caption"><a href="https://youtu.be/uX37uKdR31A" target="_blank"><br />FPGA Design Flow (Learn VHDL with Naresh Singh Dobal Series).<br /><br /></a></td></tr>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt;">
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<u><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt;">Design
Specification –</span></u><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> Design specification is the state
at which we define the important parameters like – consider a system / design
of counter then specify start point, end point, length of counter, should have
synchronous reset, reset is at logic high, at reset output should be ‘0’ etc.</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Design specification include Market
Requirement Documents (MRD Sheet), High Level Design, Low / Micro Level Design
and RTL Coding Part.</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Design specification process starts
from the MRD Sheet (Market Requirement Documents), This outlines the
requirements of a new product. This section covers the market needs, the
customer value proposition, and product functionality. It is developed by the
marketing team and upper level management.</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></div>
<br />
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>High Level Design (HLD) -</u> At this state we defined all the major
blocks of any complex system and also defines how they communicate or connected
to each other like consider a microcontroller then the major block ay be RAM,
ROM, Micro-Processor, Timer, Ports, ADC, Counters, etc.</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>Low Level Design (LLD) -</u> At this state we describes that how all major
blocks of main system / design will be implement. It contains details of State
Machines, Counters, MUX, Decoders, Internal registers etc. This phase need a
lot of time to implement.</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>RTL Coding -</u><u> </u> At
this stage we convert our micro design into HDL (VHDL / </span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> HDL) code using synthesizable
constructs of language. This part consist of coding.</span></div>
<br />
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">In real life RTL Code means that how
the small modules and components are connected to each other or how data flows
threw registers but in HDL language any code or collection of statements that
are synthesizable are called RTL code.</span></div>
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</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></div>
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<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; unicode-bidi: embed; vertical-align: baseline;">
<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>Design Simulation -</u>
Simulation is the process of verifying the functional specification of
system. We use simulators for simulation purpose. To test weather the RTL code
meets the functional specification or not, we must see all the RTL block are
functioning correctly with all the possibilities. For that purpose we use test
benches. This takes 60 – 70 %of time in design verification. </span><br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEheQ1qloVwimG-HxsU6d6pKItoSUrBemgpRokuiDR_AdfxWsi2vqEbE3RdoL5QRe1JEOkHCJNeGfLbdel9msU_RcNNkpHbo7wPYOc5xHHsj7tAKlTSqAjQZlXHk8380m9qa1iuTvPfWtzvT/s1600/img11-8-2013-3.28.56+PM.jpg" style="margin-left: auto; margin-right: auto;"><img border="0" height="244" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEheQ1qloVwimG-HxsU6d6pKItoSUrBemgpRokuiDR_AdfxWsi2vqEbE3RdoL5QRe1JEOkHCJNeGfLbdel9msU_RcNNkpHbo7wPYOc5xHHsj7tAKlTSqAjQZlXHk8380m9qa1iuTvPfWtzvT/s320/img11-8-2013-3.28.56+PM.jpg" width="320" /></a></td></tr>
<tr><td class="tr-caption"><a href="https://youtu.be/uX37uKdR31A" target="_blank">Design Simulation : Learn VHDL with Naresh Singh Dobal Series</a></td></tr>
</tbody></table>
</div>
<br />
<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; unicode-bidi: embed; vertical-align: baseline;">
<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Simulation are mainly two types.</span></div>
<br />
<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; unicode-bidi: embed; vertical-align: baseline;">
<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">First is Functional Simulation or
Behavior Simulation – Functional simulation is the verification of
functionality in the term of waveforms without considering timing
specification.</span></div>
<br />
<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; unicode-bidi: embed; vertical-align: baseline;">
<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Timing Simulation or SDF Simulation
– Timing simulation also called Gate level simulation needs complete synthesis,
place and route and timing details. In Timing simulation we consider all the
timing and other parameters for real time simulation by considering delay of
all Gate level </span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">netlist</span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">.</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></div>
<br />
<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; unicode-bidi: embed; vertical-align: baseline;">
<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>Synthesis -</u> Synthesis is the process in which synthesis
tool like design compiler (Xilinx XST or </span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">vivado</span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> etc), take RTL in </span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> or VHDL, and convert that code into the Register Level </span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Netlist</span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> according to target technology.</span><br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgeNwoq346VElBvCBxpqWInMJw4FGd7NRRnO8_a_X4PHQdHtHbOol7ceB-9gNKHyw7gY31nbZ59Z9OlM6KGV3AGPG5lwqSIQSYoHjhqnjW9topXovnsaYEkWWinjsNimsLXFT2e8N-k7tle/s1600/img11-8-2013-3.30.00+PM.jpg" style="margin-left: auto; margin-right: auto;"><img border="0" height="242" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgeNwoq346VElBvCBxpqWInMJw4FGd7NRRnO8_a_X4PHQdHtHbOol7ceB-9gNKHyw7gY31nbZ59Z9OlM6KGV3AGPG5lwqSIQSYoHjhqnjW9topXovnsaYEkWWinjsNimsLXFT2e8N-k7tle/s320/img11-8-2013-3.30.00+PM.jpg" width="320" /></a></td></tr>
<tr><td class="tr-caption"><a href="https://youtu.be/uX37uKdR31A" target="_blank">Design Synthesis : Learn VHDL with Naresh Singh Dobal Series.</a></td></tr>
</tbody></table>
</div>
<br />
<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; unicode-bidi: embed; vertical-align: baseline;">
<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Formal Verification – Check if the
RTL to gate mapping is correct.</span></div>
<br />
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Scan Insertion – Insert the scan
chain in case of ASIC.</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>Place & Route -</u><u> </u> The gate – level </span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">netlist</span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> from the synthesis tool is taken
and imported into place & route tool in </span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">verilog</span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> or </span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">vhdl</span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> </span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">netlist</span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> format, all the flip flops and
gates are placed and routed according to place and route (PNR) tool, P&R
tool generate GDS file used by foundry for ASIC Verification.</span></div>
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<span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>Configuration -</u>
This is the Implementation stage where we configure our FPGA Devices
according to our requirement or RTL Structures. Now the configured
device ready for real life testing and application use. </span></div>
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</span></div>
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<u><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Post </span><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Sil</span></u><span style="color: black; font-family: Arial; font-size: 12pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>. Validation </u>– Once the chip is back from fabrication, It
need to put in real environment for testing before sending it to market. Se we
need post silicon validation step.</span></div>
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<div dir="ltr" trbidi="on"><b><span style="font-size: medium;">Youtube : <a href="https://www.youtube.com/@Learnandgrowcommunity">https://www.youtube.com/@Learnandgrowcommunity</a></span></b></div><div dir="ltr" trbidi="on"><b><span style="font-size: medium;">LinkedIn Group : <a href="https://www.linkedin.com/groups/7478922/">https://www.linkedin.com/groups/7478922/</a></span></b></div><div dir="ltr" trbidi="on"><b><span style="font-size: medium;">Blog : <a href="https://learnandgrowcommunity.blogspot.com/">https://learnandgrowcommunity.blogspot.com/</a></span></b></div><div dir="ltr" trbidi="on"><b><span style="font-size: medium;">Facebook : Follow #learnandgrowcommunity</span></b></div><div dir="ltr" trbidi="on"><b><span style="font-size: medium;">Twitter Handle : <a href="https://twitter.com/LNG_Community">https://twitter.com/LNG_Community</a></span></b></div><div dir="ltr" trbidi="on"><b><span style="font-size: medium;">DailyMotion : <a href="https://www.dailymotion.com/LearnAndGrowCommunity">https://www.dailymotion.com/LearnAndGrowCommunity</a></span></b></div><div dir="ltr" trbidi="on"><b><span style="font-size: medium;">Instagram Handle : <a href="https://www.instagram.com/learnandgrowcommunity/">https://www.instagram.com/learnandgrowcommunity/</a></span></b></div>
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Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com1tag:blogger.com,1999:blog-8218552835565709409.post-44768285211445147052013-10-12T18:33:00.003+05:302013-10-12T18:33:59.298+05:30What a Designer can do using VHDL -<div dir="ltr" style="text-align: left;" trbidi="on">
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<b><u><span style="background-color: #f9cb9c; font-size: large;">What a Designer can do using VHDL -</span></u></b><br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiJy6mP_Di6v9mtcw2YKoCOISOyzn-m5kGoU7YLZGKsjnYQ-joCyDMGWqhdwSlyX4H_iksp0tevDYleYCZtcVhtZRH7SK9cW-DT5-v5UpqU17KZjMPihMei9I_lmf552dd300sb1RoJKrQ7/s1600/img10-12-2013-6.23.16+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiJy6mP_Di6v9mtcw2YKoCOISOyzn-m5kGoU7YLZGKsjnYQ-joCyDMGWqhdwSlyX4H_iksp0tevDYleYCZtcVhtZRH7SK9cW-DT5-v5UpqU17KZjMPihMei9I_lmf552dd300sb1RoJKrQ7/s1600/img10-12-2013-6.23.16+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span style="color: #222222; font-family: Arial, Verdana; font-size: 11px; line-height: 20px;">What a Designer can do using VHDL : (Learn VHDL with Naresh Singh Dobal series).</span></td></tr>
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<b><span style="font-family: Arial; font-size: 12pt;">Now
next thing is What you can do</span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"> with the Help of HDL’s-</span></b></div>
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<b><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">So here, I should say that you can
design a complete digital system and electronics system using HDL’s, You
can design any type of circuits like a complete robot system, a home
automation system, security system, life style appliances, Industry automation
system, PLC’s </span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">etc</span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">, even you can design a microprocessor
or a micro-controller of your own configuration according to your requirement,
you can design a computer on chip etc.</span></b></div>
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<b><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">Second most widely used application
of HDL’s are in Application domain, Here you can directly configure your design or system on Hardware with
the help of PLD’s, There are multiple type and class of PLD’s like PAL
(Programmable Array Logic), PLA (Programmable Logical Array). SPLD (Simple
Programmable Logical Devices), CPLD (Complex Programmable Logical Devices), </span><span style="font-family: Arial; font-size: small;">PROM (Programmable ROM), FPGA
(Field Programmable Gate Array), ASIC ( Application Specific Integrated
Circuit). Among these FPGA & ASIC are widely used for configuration. That
means with the help of FPGA devices we can directly configure our system on
Hardware and can test our design in real time environment. We will </span><span style="font-family: Arial;">discuss more thing about PLD's Later in our series.</span><span style="font-family: Arial; font-size: small;"> </span></b></div>
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<span style="font-family: Arial; font-size: 12pt; font-weight: bold;">Kindly share your comments, ideas, questions or suggestions to make this series interactive and more informative.</span></div>
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<span style="font-family: Arial; font-size: 12pt; font-weight: bold;">Contact US -</span></div>
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<span style="font-family: Arial; font-size: 12pt; font-weight: bold;">Naresh Singh Dobal</span><span style="font-family: Arial; font-size: 12pt;"><br /></span><span style="font-family: Arial; font-size: 12pt; font-weight: bold;">nsdobal@gmail.com</span></div>
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Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com0tag:blogger.com,1999:blog-8218552835565709409.post-686997622750760182013-10-12T18:22:00.002+05:302013-10-12T18:35:04.016+05:30What is the need of HDL in Designing of Today's Complex Structures -<div dir="ltr" style="text-align: left;" trbidi="on">
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<b><u style="background-color: #f9cb9c;"><span style="font-size: large;">What is the Need of HDL in Designing of Today's Complex Structures -</span></u></b><br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZOFd3iaygNeI-gfwFWRobqLUf0kcvpPE-ER7jOYqfr55uFRN_Trn590J5mHymPvKR5vbBz6uNN7istQPH2wErPLMd4AMohxuDWgVU9lzRkp8enXUp4WTZQXmYhHvwCmqKfgMURhGcRyo1/s1600/img10-12-2013-6.15.00+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZOFd3iaygNeI-gfwFWRobqLUf0kcvpPE-ER7jOYqfr55uFRN_Trn590J5mHymPvKR5vbBz6uNN7istQPH2wErPLMd4AMohxuDWgVU9lzRkp8enXUp4WTZQXmYhHvwCmqKfgMURhGcRyo1/s1600/img10-12-2013-6.15.00+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span style="color: #222222; font-family: Arial, Verdana; font-size: 11px; line-height: 20px;">What is the need of HDL Languages : (Learn VHDL with Naresh Singh Dobal series).</span></td></tr>
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<b><span style="font-family: Arial; font-size: 12pt;"> This
is the most Important Question ever, that</span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"> Why we need of HDL’s, and what we
loose without HDL’s?</span></b></div>
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<span style="vertical-align: baseline;"><span style="font-family: Arial; font-size: small;"><b> For giving the answer of that
question more </b></span><b><span style="font-family: Arial;">effectively</span><span style="font-family: Arial; font-size: small;"> I am going few decades back, As
we discussed previously in early circuit designing (manual designing) or In
late of 70’s the circuit designers designed their system with the help of truth
tables, Boolean mathematics, K-maps and other expression solving techniques.
But chip density and complexity was increasing continuously and then thousands of gates in a single chip
was common and for designing that system was not the easy task for engineers.
So Researchers planned some new techniques for designing and verification and
invented a totally different concept called HDL
Based Designing and Verification. And second thing early designer and
verification engineers worked on the Printed Circuit Boards or on Bread Boards
for test and verify their designs, but that was not the practical approach to
verify designs because that takes too much time and also the verification
engineers was not sure about the verification. There are multiple reasons
behind that like if engineer used 1000 gates in verification that first he have
to check the response of all the 1000 gates, because if any one of the gates
not works properly then we may get the wrong result. That means each gate must
be checked before using in logical verification which was not practically
possible.</span></b></span><b><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"> </span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">That means testing of large
circuits was not possible because the large circuits contain lots of gates and
the response of each and every gate could not be checked.</span></b></div>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b>Second thing the time needed for
logical designing, In early days or in manual designing a large team was needed
for designing and more time was needed. After using of HDL’s designing time was
shorted because HDL’s are ready to work on sequential execution of statements
and the designers only have to write their requirements in the term of language
and then synthesis tools convert that High level language into Structural or
RTL level or Gate level Design. Hence using HDL’s Circuit Designing was very
easy through computer and then we can also develop these codes on hardware
using PLD’s. and save time and money.</b></span></div>
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<span style="font-family: Arial; font-size: 12pt; font-weight: bold;">Kindly
share your comments, ideas, questions or suggestions to make this series
interactive and more informative.</span></div>
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<span style="font-family: Arial; font-size: 12pt; font-weight: bold;">Contact
US -</span></div>
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<span style="font-family: Arial; font-size: 12pt; font-weight: bold;">Naresh
Singh Dobal</span><span style="font-family: Arial; font-size: 12pt;"><br />
</span><span style="font-family: Arial; font-size: 12pt; font-weight: bold;">nsdobal@gmail.com</span></div>
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Learn And Grow Communityhttp://www.blogger.com/profile/04266102975906928137noreply@blogger.com0tag:blogger.com,1999:blog-8218552835565709409.post-74850293727342500612013-10-12T10:13:00.001+05:302013-10-12T18:34:21.079+05:30Summary : Brief History about VHDL<div dir="ltr" style="text-align: left;" trbidi="on">
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<b><u><span style="background-color: #f9cb9c; font-size: large;">Summary : A Brief History about VHDL -</span></u></b><br />
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<tr><td class="tr-caption" style="text-align: center;">Summary : History about VHDL (Learn VHDL with Naresh Singh Dobal Series).</td></tr>
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<b><u style="background-color: #f9cb9c;"><span style="font-family: Arial; font-size: 12pt;">Summary</span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">
about History of VHDL –</span></u></b><br />
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<ul style="text-align: left;">
<li><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">According to the records VHDL was
initially initiated by US- </span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">DoD</span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">
(United State – Department of Defense), They have initiated VHDL to design
there complex architectures of electronics used in defense. But later this was
transferred to IEEE for standardization.</span></li>
<li><span style="font-family: Arial; font-size: 12pt;">In 1985 All the rights of VHDL was
transferred to IEEE.</span></li>
<li><span style="font-family: Arial; font-size: 12pt;">After two years in 1987 IEEE
launched VHDL standards.</span></li>
<li><span style="font-family: Arial; font-size: 12pt;">In 1994 Revised edition of VHDL
Standard was published which was named by VHDL 1076-1993.</span></li>
<li><span style="font-family: Arial; font-size: 12pt;">In 2000 again Revised Edition of
standard was launched and named by VHDL 1076-2000.</span></li>
<li><span style="font-family: Arial; font-size: 12pt;">VHDL 1076-2002 was published in
year 2002.</span></li>
<li><span style="font-family: Arial; font-size: 12pt;">VHDL 1076-2007 was published in
year 2007.</span></li>
<li><span style="font-family: Arial; font-size: 12pt;">Recently in year 2009 VHDL revised
edition VHDL 1076-2008 was published.</span></li>
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<span style="font-family: Arial; font-size: 12pt;">Kindly
share your suggestions,</span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"> queries, comments or questions to make
this series more interactive and informative.</span></div>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b>Contact US -</b></span></div>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b>Naresh Singh Dobal</b></span></div>
<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; unicode-bidi: embed; vertical-align: baseline;">
<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b>nsdobal@gmail.com</b></span></div>
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