Tuesday, 19 November 2013

VHDL Lab Exercise :: Exercise 1






VHDL Lab Exercise   :::   Exercise 1 -


LAB 1:  COMBINATIONAL SYSTEM DESIGN USING BASIC GATES AND EQUATIONS.
VHDL Lab Exercise 1 :: VHDL with Naresh Singh Dobal Learning Series.




Task1 :   Write a VHDL Program for all Logic Gates.
Task2 :   Write a VHDL code for a Half Adder using Digital Electronics.
Task3 :   Write a VHDL code for a Full Adder using Digital Electronics.
Task4 :   Write a VHDL code for a Half Subtractor using Digital Electronics.
Task5 :   Write a VHDL code for a Full Subtractor using Digital Electronics.
Task6:    Write a VHDL code for a 4:1 Multiplexer using Digital Electronics.
Task7:    Write a VHDL code for a 1:4 Multiplexer using Digital Electronics.
Task8:    Write a VHDL code for a 4:2 Encoder using Digital Electronics.
Task9:    Write a VHDL code for a 2:4 Decoder using Digital Electronics.
Task10:  Write a VHDL code for 1 bit Comparator using Digital Electronics. 


If you feel any difficulties in any assignment then follow the below link...



I would love to read your suggestions and comments here below.
My name is Naresh Singh Dobal, for any query contact me at nsdobal@gmail.com

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