How to write Codes in Structural Modeling Style in VHDL

Syntax -

Component Declaration -


COMPONENT  component_name  IS
        PORT (     
                    List of Interface Ports
                   );
END COMPONENT Component_name; 


Sample -

component     component_name
       port    (port_signal_names :    mode    type ;
                   port_signal_names :    mode    type ;
                    .
                    .
                    port_signal_names :    mode    type );
end component ; 
                            



Component Instantiation -

Component_label    :     Instance_name    PORT MAP    (Association-list) ;

• Component_label can be any legal identifier and considered as the name of the instance.
• Instance_name must be the name of a component declared earlier using a component declaration.

Methods of Component Instantiations -

• Positional Mapping.
• Nominal Mapping.

Positional Mapping. -   

Example -

u0 : dff       PORT MAP    (clk  ,   reset    ,   din   ,    dout );

Sequence of Formal ports must be same with sequence of Actual Ports of component.



Nominal Mapping -

Example -

u0 : dff      PORT MAP     ( clk  =>  clk   ,  
                                            reset   =>   reset    ,
                                             din   =>   din,
                                                  dout   =>   dout )   ;


No need to consider the sequence of Formal ports and Actual Ports.



 Sample Programs-

• Design of 2  to  1  Multiplexer using Structural Modeling Style. (VHDL Code).
• Design of 4 Bit Adder using 4 Full Adder (Structural Modeling Style). (VHDL Code).
• Design of 4 Bit Subtractor using Structural Modeling Style. (VHDL Code).
• Design of 4 Bit Adder cum Subtractor using Structural Modeling Style (VHDL Code).
• Design of 4 Bit Adder cum Subtractor using XOR Gate & Structural Modeling Style (VHDL Code).

Flip Flop Design using Structural Modeling Style-

• Design of Toggle Flip Flop using  D-Flip Flop (Structural Modeling Style) (VHDL Code).
• Design of Master Slave Flip Flop using D-Flip Flop (Structural Modeling Style) (VHDL Code).
• Design of Toggle Flip Flop using J-K Flip Flop (Structural Modeling Style) (VHDL Code).

Shift Registers Design using Structural Modeling Style-

• 4 - Bit Serial In - Serial Out Design Using Structural Modeling Style. (VHDL Code).
• 4 - Bit Serial In - Parallel Out Design Using Structural Modeling Style. (VHDL Code).
• 4 - Bit Parallel In - Parallel Out Design Using Structural Modeling Style. (VHDL Code).

• 4 - Bit Stack Design using Structural Modeling Style (VHDL Code).
• 4 - Bit Queue Design using Structural Modeling Style (VHDL Code).