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Monday, July 29, 2013

Design of Parallel In - Serial OUT Shift Register using Behavior Modeling Style (VHDL Code).






Design of Parallel IN - Serial OUT Shift Register using Behavior Modeling Style -

Output Waveform : Parallel IN - Serial OUT Shift Register





VHDL Code-




-------------------------------------------------------------------------------
--
-- Title       : parallel_in_serial_out
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Parallel IN - Serial OUT Shift Register.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity parallel_in_serial_out is
     port(
         clk : in STD_LOGIC;
         reset : in STD_LOGIC;
         load : in STD_LOGIC;
         din : in STD_LOGIC_VECTOR(3 downto 0);
         dout : out STD_LOGIC
         );
end parallel_in_serial_out;


architecture piso_arc of parallel_in_serial_out is
begin

    piso : process (clk,reset,load,din) is
    variable temp : std_logic_vector (din'range);
    begin
        if (reset='1') then
            temp := (others=>'0');
        elsif (load='1') then
            temp := din ;
        elsif (rising_edge (clk)) then
            dout <= temp(3);
            temp := temp(2 downto 0) & '0';
        end if;
    end process piso;

end piso_arc;

9 comments:

  1. Hello Sir, if I want to increase the input of PISO to 8 inputs (0 to 7), where the code that I must modify...?

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;

    entity parallel_in_serial_out is
    port(
    clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    load : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR(7 downto 0);
    dout : out STD_LOGIC
    );
    end parallel_in_serial_out;


    architecture piso_arc of parallel_in_serial_out is
    begin

    piso : process (clk,reset,load,din) is
    variable temp : std_logic_vector (din'range);
    begin
    if (reset='1') then
    temp := (others=>'0');
    elsif (load='1') then
    temp := din ;
    elsif (rising_edge (clk)) then
    dout <= temp(7);
    temp := temp(6 downto 0) & '0';
    end if;
    end process piso;

    end piso_arc;

    thank you

    ReplyDelete
  2. how to design a series piso ??

    ReplyDelete
  3. how to write a vhdl code for push in bus out shift register?

    ReplyDelete
  4. piso structural code here

    ////dff entity
    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.std_logic_unsigned.all;
    use IEEE.std_logic_arith.all;

    entity dff is
    port(d,clk,reset: in std_logic;q,qbar: out std_logic);
    end dff;

    architecture champ of dff is
    begin
    process(clk,d,reset)
    variable x:std_logic:='0';
    begin

    if(clk'event and clk='1')then
    case reset is
    when '1'=> x:='0';
    when '0'=>
    if(d='0')then x:='0';
    elsif(d='1')then x:='1';
    end if;
    when others=>NULL;
    end case;
    end if;
    q<=x;
    qbar<=not(x);
    end process;
    end champ;
    ///piso sturtural entity
    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.std_logic_unsigned.all;
    use IEEE.std_logic_arith.all;

    entity pisoregstr is
    port(din: in std_logic_vector(3 downto 0);clk,reset,shift: in std_logic;q,qbar: out std_logic);
    end pisoregstr;

    architecture champ of pisoregstr is

    component dff
    port(d,clk,reset: in std_logic;q,qbar: out std_logic);
    end component;

    component or1
    port(a,b: in std_logic;cout: out std_logic);
    end component;

    component and2
    port(a,b: in std_logic;cout: out std_logic);
    end component;

    component not2
    port(a: in std_logic;cout: out std_logic);
    end component;

    signal qns,qnsbar: std_logic_vector(2 downto 0);
    signal load: std_logic;
    signal g1,g2,g3,g4,g5,g6: std_logic;
    signal d2,d3,d4: std_logic;

    begin
    F1: dff port map (din(0),clk,reset,qns(0),qnsbar(0));--FF1

    N1: not2 port map (shift,load);
    A1: and2 port map (qns(0),shift,g4);
    A2: and2 port map (din(1),load,g1);
    O1: or1 port map (g4,g1,d2);

    F2: dff port map (d2,clk,reset,qns(1),qnsbar(1));--FF2

    A3: and2 port map (qns(1),shift,g5);
    A4: and2 port map (din(2),load,g2);
    O2: or1 port map (g2,g5,d3);

    F3: dff port map (d3,clk,reset,qns(2),qnsbar(2));--FF3

    A5: and2 port map (qns(2),shift,g6);
    A6: and2 port map (din(3),load,g3);
    O3: or1 port map (g3,g6,d4);

    F4: dff port map (d4,clk,reset,q,qbar);


    end champ;


    If any one need this


    ReplyDelete
  5. Replies
    1. ampersand '0' or & '0' is to signify the new input that is to be appended to the register. For example if the register contains 101011, after performing left shift, '1' or the MSB is pushed out of the register while '0' becomes the new LSB and each digit shifts to the next position on the left...so the register now contains 010110 and '1' is at the result at output

      Delete
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