Design of 1 : 4 Demultiplexer using with-select Concurrent Statement (VHDL Code).

Design of 1 : 4 Demultiplexer using with-select Concurrent Statement (Data Flow Modeling Style)-

Output Waveform : 1 : 4 Demultiplexer

Program -


-------------------------------------------------------------------------------
--
-- Title       : demultiplexer1_4
-- Design      : vhdl_test
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
--
-- File        : 1 : 4 Demultiplexer using with select.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity demultiplexer1_4 is
     port(
         din : in STD_LOGIC;
         sel : in STD_LOGIC_VECTOR(1 downto 0);
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end demultiplexer1_4;

architecture demultiplexer1_4_arc of demultiplexer1_4 is
begin

    with sel select
    dout <= (din & "000") when "00",
            ('0' & din & "00") when "01",
            ("00" & din & '0') when "10",
            ("000" & din) when others;

end demultiplexer1_4_arc;